PA28F400BVB120 Intel, PA28F400BVB120 Datasheet

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... Block. Reference Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family datasheet, order number 290580. For new designs with this device, Intel recommends using the 4-Mbit Smart 5 Boot Block. Reference CC Smart 5 Flash Memory Family Mbit datasheet, order number 290599. These documents are also available at Intel’s website, http://www.intel.com/design/flcomp. ...

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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...

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... Temperature Operations............................45 4.12 AC Characteristics—Read Only Operations—Extended Temperature .........51 4.13 AC Characteristics—WE# Controlled Write Operations—Extended Temperature .........52 4.14 AC Characteristics—CE# Controlled Write Operations—Extended Temperature .........54 4.15 Erase and Program Timings—Extended Temperature..............................................55 5.0 ORDERING INFORMATION..........................56 6.0 ADDITIONAL INFORMATION .......................57 Related Intel Information ..................................57 PAGE 3 ...

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... Applying V voltages (Sections 5.1 and 6.1) rewritten for clarity. CC Minor cosmetic changes/edits. -004 Corrections: Spec typographical error “t Intel386™ EX Microprocessor block diagram updated because latest Intel386 CPU specs require less glue logic. Spec t and t changed from 5 ns (max (min). ELFL ...

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... PP pin from V line writes are desired. PP 1.2 Main Features Intel’s SmartVoltage technology is the most flexible voltage solution in the flash industry, providing two discrete voltage supply pins: V read operation, and V for program and erase PP operation. Discrete supply pins allow system designers to use the optimal voltage levels for their design ...

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... CUI. Data writes are performed in word (28F400 family) or byte (28F400 or 28F004B families) increments. 6 SEE NEW DESIGN RECOMMENDATIONS Each byte or word in the flash memory can be PP programmed independently locations, unlike erases, which erase all locations within a block simultaneously. ...

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... Kbytes each for frequently updated data storage and diagnostic messages (e.g., phone numbers, authorization codes). become Intel’s boot block architecture provides a flexible voltage solution for the different design needs of various applications. The asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. The boot block provides a secure boot PROM ...

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... A data bus buffer may be needed for processor speeds above 25 MHz. Figure 1. 28F400 Interface to Intel386™ EX Microprocessor A[16:18 80C188EB ALE AD - UCS# WR# RD# RESIN# System Reset P1.X P1.X Figure 2. 28F004B Interface to Intel80C188EB 8-Bit Embedded Microprocessor 8 SEE NEW DESIGN RECOMMENDATIONS A[0:17] CE# OE# WE# 28F400BV-60 DQ[0:15] RP# ADDRESS LATCHES 28F004-T ADDRESS LATCHES ...

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SmartVoltage BOOT BLOCK FAMILY 28F800 28F200 ...

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... OUTPUT during a Program command. Inputs commands to the CUI when CE# and WE# are active. Data is internally latched during the write cycle. Outputs array, intelligent identifier and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. DQ –DQ ...

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SmartVoltage BOOT BLOCK FAMILY Table 2. 28F400/004 Pin Descriptions (Continued) Symbol Type WP# INPUT WRITE PROTECT: Provides a method for unlocking the boot block in a system without supply. When WP logic low, the ...

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... EEPROM. By using software techniques, the byte- rewrite functionality of EEPROMs can be emulated. These techniques are detailed in Intel’s application note, AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM . Each boot block component contains two parameter blocks of 8 Kbytes (8,192 bytes) each. The parameter blocks are not write-protectable ...

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SmartVoltage BOOT BLOCK FAMILY 28F400-T 3FFFFH 16-Kbyte BOOT BLOCK 3E000H 8-Kbyte PARAMETER BLOCK 3DFFFH 3D000H 8-Kbyte PARAMETER BLOCK 3CFFFH 3C000H 3BFFFH 96-Kbyte MAIN BLOCK 30000H 2FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 128-Kbyte MAIN BLOCK 10000H 0FFFFH 128-Kbyte MAIN BLOCK ...

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... V allows write and erase of the device. All PP functions associated with altering memory contents: Program and Erase, Intelligent Identifier Read, and Read Status are accessed via the CUI. The internal Write State Machine (WSM) completely automates program and erase, beginning operation signaled by the CUI and reporting status through the status register ...

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... SmartVoltage BOOT BLOCK FAMILY Table 3. Bus Operations for Word-Wide Mode (BYTE Mode Notes RP# Read 1,2 Output Disable V IH Standby V IH Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier 4 (Device) Write 6,7 Table 4. Bus Operations for Byte-Wide Mode (BYTE Mode Notes RP# CE# ...

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... INTELLIGENT IDENTIFIERS To read the manufacturer and device codes, the device must be in intelligent identifier read mode, which can be reached using two methods: by writing the Intelligent Identifier command (90H taking the A pin Once in intelligent 9 ID identifier read mode outputs the manu- 0 facturer’ ...

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... SmartVoltage BOOT BLOCK FAMILY Table 6. Command Codes and Descriptions Code Device Mode 00 Invalid/ Unassigned commands that should not be used. Intel reserves the right to redefine Reserved these codes for future functions. FF Read Array Places the device in read array mode, so that array data will be output on the data pins ...

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... SRD - Data read from status register. 4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and device codes Address within the block being erased Address to be programmed Data to be programmed at location PA. ...

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SmartVoltage BOOT BLOCK FAMILY Table 8. Status Register Bit Definition WSMS ESS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready (WSMS Busy SR.6 = ERASE-SUSPEND STATUS (ESS Erase Suspended 0 ...

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... The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming however, reads from the memory array or intelligent identifier cannot be accomplished until the CUI is given the appropriate command. 3.3.4 ERASE MODE To erase a block, write the Erase Set-Up and Erase Confirm commands to the CUI, along with the addresses identifying the block to be erased ...

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... The truth table, Table 9, clearly defines the write protection methods. 3.4 FOR COMPLETE PP IL PROTECTION For complete write protection of all blocks in the flash device, the V programming voltage can be PP held low. When V is below V , any program or PP PPLK erase operation will result in a error in the status register. ...

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Start Write 40H, Word/Byte Address Write Word/Byte Data/Address Read Status Register NO SR YES Full Status Check if Desired Word/Byte Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3= V Range Error ...

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SmartVoltage BOOT BLOCK FAMILY Start Write 20H, Block Address Write D0H and Block Address Read Status Register Suspend Erase Loop NO 0 YES Suspend SR.7 = Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK ...

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Start Write B0H Write 70H Read Status Register 0 SR SR.6 = Erase Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Erase Resumed Read Array Data Figure 11. Erase Suspend/Resume ...

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... CPU initialization would not occur because the flash memory may be providing status information instead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset by connecting the RP# pin to the same RESET# signal that resets the system CPU. ...

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... CUI must be reset to read array mode PPLK via the Read Array command if accesses to the flash memory are desired. Please refer to Intel’s application note AP-617 Additional Flash Data Protection Using V and WP#, for a circuit-level description of how to implement the protection discussed in Section 3.6. ...

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... NOTICE: This datasheet contains preliminary information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" ...

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APPLYING V CC VOLTAGES When applying V voltage to the device, a delay CC may be required before initiating device operation, depending on the V ramp rate slower than 1V/100 µs (0.01 V/µs) then no delay ...

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SmartVoltage BOOT BLOCK FAMILY 4.4 DC Characteristics—Commercial Prod Sym Parameter V CC Note I Input Load Current Output Leakage Current Standby Current 1,3 CC CCS I V Deep Power-Down 1 CC CCD ...

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... I V Erase Current 1,4 PP PPE V Erase PPES Suspend Current I RP# Boot Block Unlock 1,4 RP# Current A Intelligent I 9 1,4 ID Identifier Current SEE NEW DESIGN RECOMMENDATIONS 4-MBIT SmartVoltage BOOT BLOCK FAMILY (Continued) BV-60 BV-80 BV-120 3.3 ± 0 ± 10% Unit Typ Max Typ Max ...

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... SmartVoltage BOOT BLOCK FAMILY 4.4 DC Characteristics—Commercial Prod Sym Parameter Note V A Intelligent Identifier 9 ID Voltage V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage Output High Voltage (TTL Output High Voltage (CMOS Lock-Out Voltage PP PPLK (Prog/Erase Operations) ...

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INPUT 1.5 0.0 NOTE: AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% ...

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SmartVoltage BOOT BLOCK FAMILY 4.5 AC Characteristics—Read Only Operations—Commercial Prod Sym Parameter V CC Load Note t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay 2 ELQV t RP# to Output Delay ...

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AC Characteristics—Read Only Operations—Commercial Prod Sym Parameter V CC Load Notes t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay 2 ELQV t RP# to Output Delay PHQV t OE# to Output ...

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SmartVoltage BOOT BLOCK FAMILY Device and Address Selection V IH ADDRESSES (A) Address Stable CE# ( OE# ( WE# ( High Z DATA ...

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AC Characteristics—WE# Controlled Write Operations Sym Parameter t Write Cycle Time AVAV t RP# Setup to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t Boot Block Lock Setup to WE# PHHWH Going High V ...

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SmartVoltage BOOT BLOCK FAMILY 4.6 AC Characteristics—WE# Controlled Write Operations (Continued) Prod Sym Parameter V CC Load Notes t Write Cycle Time AVAV t RP# Setup to WE# Going PHWL Low t CE# Setup to WE# Going ELWL Low ...

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NOTES: 1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC Characteristics during read mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes ...

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SmartVoltage BOOT BLOCK FAMILY 4.7 AC Characteristics—CE# Controlled Write Operations Sym Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# PHEL Going Low t WE# Setup to CE# Going Low WLEL t Boot Block Lock Setup ...

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AC Characteristics—CE# Controlled Write Operations (Continued) Prod Sym Parameter V CC Load Notes t Write Cycle Time AVAV t RP# High Recovery to PHEL CE# Going Low t WE# Setup to CE# Going WLEL Low 6,8 t Boot Block ...

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SmartVoltage BOOT BLOCK FAMILY NOTES: See AC Characteristics—WE# Controlled Write Operations for notes 1 through 11. 12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE# defines the write ...

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... See Note 3 for typical conditions Typical conditions are +25 °C with V and 5 12.0 V typically results in a 60% reduction in programming time Contact your Intel field representative for more information. 4.9 Extended Operating Conditions Table 11. Extended Temperature and V Symbol Parameter T Operating Temperature A V 2.7 V–3 Supply Voltage ...

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SmartVoltage BOOT BLOCK FAMILY 4.9.1 APPLYING V CC VOLTAGES When applying V voltage to the device, a delay CC may be required before initiating device operation, depending on the V ramp rate slower than 1V/100 µs ...

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DC Characteristics—Extended Temperature Operations Prod TBE-120 Sym Parameter V 2.7 V–3 Notes Typ Max I Input Load 1 ± 1.0 IL Current I Output 1 ± Leakage Current V I 1,3 50 110 CC CCS ...

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SmartVoltage BOOT BLOCK FAMILY 4.11 DC Characteristics—Extended Temperature Operations Prod TBE-120 Sym Parameter V 2.7 V–3 Notes Typ Max CCW Program Current for Word Byte V Erase I ...

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... PP PPES Suspend Current I RP# Boot 1,4 500 RP# Block Unlock Current A I 1,4 500 9 ID Intelligent Identifier Current SEE NEW DESIGN RECOMMENDATIONS 4-MBIT SmartVoltage BOOT BLOCK FAMILY (Continued) TBV-80 TBV-80 TBE-120 3.3 ± 0 ± 10% Unit Test Conditions Typ Max Typ Max ...

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... SmartVoltage BOOT BLOCK FAMILY 4.11 DC Characteristics—Extended Temperature Operations Prod TBE-120 Sym Parameter V 2.7 V–3 Notes Min Max A V 11.4 12 Intelligent Identifier Voltage V Input Low –0.5 0.8 IL Voltage V V Input High 2 ± Voltage 0.5V V Output Low 0.45 OL Voltage V 1 Output 2 ...

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NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at V product versions (packages and speeds specified with device de-selected. If device is read while in erase suspend, current draw is sum of I ...

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SmartVoltage BOOT BLOCK FAMILY 2.7 INPUT 1.35 0.0 NOTE: AC test inputs are driven at 2.7 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.35 V. Input ...

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AC Characteristics—Read Only Operations Sym Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# to Output Delay PHQV t OE# to Output Delay GLQV t CE# to Output ...

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SmartVoltage BOOT BLOCK FAMILY 4.13 AC Characteristics— WE#-Controlled Write Operations Extended Temperature Sym Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# PHWL Going Low t CE# Setup to WE# Going Low ELWL t Boot Block ...

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NOTES: 1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC Characteristics during read mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes ...

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SmartVoltage BOOT BLOCK FAMILY 4.14 AC Characteristics—CE#-Controlled Write Operations Temperature Sym Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# PHEL Going Low t WE# Setup to CE# Going Low WLEL t Boot Block Lock Setup ...

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... Typical conditions are +25 °C with V and 5 12.0 V typically results in a 60% reduction in programming time Contact your Intel field representative for more information. SEE NEW DESIGN RECOMMENDATIONS 4-MBIT SmartVoltage BOOT BLOCK FAMILY 12 V ± ± 10% 2.7 V–3.6 V 3.3 ± 0.3 V Max Typ Max ...

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... Density / Organization 00X = x8-only ( X00 = x8/x16 Selectable ( VALID COMBINATIONS: 40-Lead TSOP 44-Lead PSOP Commercial E28F004BVT60 PA28F400BVT60 E28F004BVB60 PA28F400BVB60 E28F004BVT80 PA28F400BVT80 E28F004BVB80 PA28F400BVB80 E28F004BVT120 PA28F400BVT120 E28F004BVB120 PA28F400BVB120 Extended TE28F004BVT80 TB28F400BVT80 TE28F004BVB80 TB28F400BVB80 TE28F004BET120 TE28F004BEB120 V CC Name 2 28F004BV 28F400BV 28F400CV 28F004BE ...

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... BV/BE Specification Update NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools. ...