PA28F004SC-85 Intel, PA28F004SC-85 Datasheet - Page 26

• Manufacturer Part Number: PA28F004SC-85
• Manufacturer: Intel

Specifications of PA28F004SC-85

• Density: 4Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
26
FULL STATUS CHECK PROCEDURE
Set Lock-Bit Successful
Set Lock-Bit Complete
Block/Device Address
Block/Device Address
Read Status Register
Check if Desired
Data (See Above)
Write 01H/F1H,
Read Status
Write 60H,
Full Status
Register
SR.4,5 =
SR.3 =
SR.1 =
SR.7 =
SR.4 =
Start
0
0
0
0
1
0
1
1
1
1
Figure 11. Set Block and Master Lock-Bit Flowchart
Device Protect Error
Command Sequence
Set Lock-Bit Error
V
PP
Range Error
Error
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation or after
Write FFH after the last lock-bit set operation to place device in
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
If error is detected, clear the Status Register before attempting retry
Operation
a sequence of lock-bit set operations.
read array mode.
Register command in cases where multiple lock-bits are set before
full status is checked.
or other error recovery.
Operation
Standby
Standby
Standby
Standby
Standby
Write
Read
Bus
Write
Bus
Command
Lock-Bit Confirm
Block or Master
Lock-Bit Setup
Block/Master
Command
Set
Set
Check SR.1
1 = Device Protect Detect
Check SR.3
1 = V
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.4
1 = Set Lock-Bit Reset Error
RP# = V
(Set Master Lock-Bit Operation)
RP# = V
(Set Block Lock-Bit Operation)
Data = 60H
Addr = Block Address (Block),
Data = 01H (Block),
Addr = Block Address (Block),
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
PP
Device Address (Master)
F1H (Master)
Device Address (Master)
Error Detect
PRELIMINARY
IH
HH
Comments
Comments
,
, Master Lock-Bit Is Set