TB28F004S5-100 Intel, TB28F004S5-100 Datasheet - Page 19

• Manufacturer Part Number: TB28F004S5-100
• Manufacturer: Intel

Specifications of TB28F004S5-100

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

PRELIMINARY
FULL STATUS CHECK PROCEDURE
Read Status Register
Check if Desired
Data (See Above)
Block Address
Block Address
Read Status
Block Erase
Write 20H,
Write D0H,
Full Status
Complete
Block Erase
Register
SR.4,5 =
Successful
SR.7 =
SR.5 =
SR.1 =
Start
SR.3 =
0
0
0
0
1
0
1
1
1
1
Command Sequence
Device Protect Error
Block Erase
No
Suspend
Figure 6. Automated Block Erase Flowchart
V
PP
Block Erase
Range Error
Error
Error
Suspend Block
Erase Loop
Yes
Operation
Repeat for subsequent block erasures.
Full status check can be done after each block erase, or after a
Write FFH after the last operation to place device in read array mode.
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
If error is detected, clear the Status Register before attempting
Operation
Standby
sequence of block erasures.
Standby
Standby
Standby
Write
Write
Read
Standby
Register command in cases where multiple blocks are erased
before full status is checked.
retry or other error recovery.
Bus
Bus
Erase Setup
Command
Confirm
Erase
Command
28F004S5, 28F008S5, 28F016S5
Check SR.3
1 = V
Check SR.1
1 = Device Protect Detect
Only required for systems
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.5
1 = Block Erase Error
Data = 20H
Addr = Within Block to be Erased
Data = D0H
Addr = Within Block to be Erased
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
RP# = V
implementing lock-bit configuration
PP
Error Detect
Comments
IH
Comments
, Block Lock-Bit Is Set
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