PA28F800BVT120 Intel, PA28F800BVT120 Datasheet - Page 39

• Manufacturer Part Number: PA28F800BVT120
• Manufacturer: Intel

Specifications of PA28F800BVT120

• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
3. Refer to command definition table for valid A
4. Refer to command definition table for valid D
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at V
7. Time t
8. Sampled, but not 100% tested.
9.
10. See Test Configuration (Figure 11), 5 V High-Speed Test component values.
11. See Test Configuration (Figure 11), 5 V Standard Test component values.
NOTES:
1. V
2. Write program or Erase Setup Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.
Characteristics during read mode.
which includes verify and margining operations.
successfully.
SEE NEW DESIGN RECOMMENDATIONS
CC
See Test Configuration (Figure 11), 3.3 V Standard Test component values.)
Power-Up and Standby.
PHBR
is required for successful locking of the boot block.
ADDRESSES (A)
Figure 14. AC Waveforms for Write Operations (WE#–Controlled Writes)
CE# (E)
OE# (G)
WE# (W)
DATA (D/Q)
RP# (P)
WP#
V
PP
6.5V
(V)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
HH
IH
IH
PPH
PPH
IL
IL
IL
IL
IL
IL
IL
PPLK
IL
t
ELWL
1
2
1
High Z
t
PHWL
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
A
t
AVAV
IN
2
D
IN
t
IN
IN
WHWL
. (Table 7)
. (Table 7)
t
WHEH
t
t
t
WLWH
DVWH
WHDX
t
AVWH
A
3
IN
D
HH
IN
t
t
PHHWH
VPWH
or WP# should be held at V
t
t
WHQV1,2,3,4
WHAX
4
5
Valid
SRD
t
t
QVVL
QVPH
IH
until operation completes
6
D
IN
0539_16
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