CY7C09389V-9AC Cypress Semiconductor Corp, CY7C09389V-9AC Datasheet - Page 4

• Manufacturer Part Number: CY7C09389V-9AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09389V-9AC

• Density: 1.125Mb
• Access Time (max): 20ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 230mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Pin Definitions
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18
dual-port static RAMs. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory
lines allow for minimal setup and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to data
valid t
be used to bypass the pipelined output register to eliminate
access latency. In flow through mode, data is available t
18 ns after the address is clocked into the device. Pipelined
output or flow through mode is selected through the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the LOW to HIGH
transition of the clock signal. The internal write pulse is self timed
to allow the shortest possible cycle times.
Document #: 38-06056 Rev. *C
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
LB
UB
OE
R/W
FT/PIPE
GND
NC
V
Note
11. When writing simultaneously to the same location, the final value cannot be guaranteed.
0L
CC
Left Port
L
0L
0L
L
L
–A
L
L
L
–I/O
, CE
CD2
15L
L
L
L
17L
1L
= 6.5 ns
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
LB
UB
OE
R/W
FT/PIPE
0R
Right Port
R
0R
0R
R
R
[1, 2]
–A
R
R
[11]
R
–I/O
,CE
15R
. Registers on control, address, and data
R
(pipelined). Flow through mode can also
R
1R
R
17R
Address Inputs (A
Address Strobe Input. Used as an address qualifier. This signal must be asserted LOW to access
the part using an externally supplied address. Asserting this signal LOW also loads the burst counter
with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
active states (CE
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower
byte. (I/O
OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow Through/Pipelined Select Input. For flow through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
0
–I/O
8
for x18, I/O
0
≤ V
0
–A
IL
14
and CE
CD1
for 32K, A
0
–I/O
0
=
–I/O
1
7
≥ V
15
for x16) of the memory array. For read operations both the LB and
0
for x16 devices).
–A
IH
A HIGH on CE
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads/writes one word from or into
each successive address location, until CNTEN is deasserted.
The counter can address the entire memory array and loop back
to the start. Counter Reset (CNTRST) is used to reset the burst
counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
).
13
for 16K devices).
Description
0
or LOW on CE
CY7C09269V/79V/89V
CY7C09369V/79V/89V
0
AND CE
0
1
LOW and CE
for one clock cycle powers down
1
8/9L
must be asserted to their
–I/O
1
15/17L
HIGH to reactivate
MAX
).
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