CY7C1354BV25-200AC Cypress Semiconductor Corp, CY7C1354BV25-200AC Datasheet - Page 19

• Manufacturer Part Number: CY7C1354BV25-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354BV25-200AC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05292 Rev. *E
Thermal Resistance
Switching Characteristics
AC Test Loads and Waveforms
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
Shaded areas contain advance information.
Notes:
16. Tested initially and after any design or process changes that may affect these parameters.
17. This part has a voltage regulator internally; t
18. t
19. At any given voltage and temperature, t
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when V
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Power
CYC
CH
CL
CO
EOV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
Parameters
MAX
Parameter
OUTPUT
initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
Q
Q
[17]
, t
JA
JC
CLZ
, t
EOLZ
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
, and t
Z
V
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BW
ADV/LD Set-up Before CLK Rise
0
CC
= 50Ω
Description
EOHZ
(typical) to the first access read or write
(a)
x
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[16]
V
Set-up Before CLK Rise
L
= 1.25V
[18, 19, 20]
[18, 19, 20]
Description
R
DDQ
L
EOHZ
Over the Operating Range
= 50Ω
= 2.5V.
power
is less than t
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.
is the time power needs to be supplied above V
[18, 19, 20]
[18, 19, 20]
Output
2.5V
INCLUDING
Test Conditions
EOLZ
JIG AND
SCOPE
and t
5 pF
CHZ
is less than t
(b)
[ 21, 22]
Min.
1.25
1.25
1.25
R=1667Ω
4.4
1.8
1.8
1.4
1.4
1.4
1.4
1.4
1
0
R = 1538Ω
-225
CLZ
BGA Typ.
Max.
to eliminate bus contention between SRAMs when sharing the same
225
2.8
2.8
2.8
2.8
25
6
V
0V
DD
DD
< 1.0 ns
minimum initially, before a Read or Write operation can be
Min.
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1
5
0
fBGA Typ.
10%
-200
90%
27
6
ALL INPUT PULSES
Max.
200
3.2
3.2
3.2
3.2
1.25V
TQFP Typ.
CY7C1354BV25
CY7C1356BV25
(c)
Min.
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
25
9
1
6
0
-166
[16]
Max.
166
3.5
3.5
3.5
3.5
°C/W
°C/W
Page 19 of 27
90%
Unit
10%
< 1.0 ns
Notes
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
17