CY7C1367A-150AC Cypress Semiconductor Corp, CY7C1367A-150AC Datasheet - Page 8

• Manufacturer Part Number: CY7C1367A-150AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AC

• Density: 9Mb
• Access Time (max): 3.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 380mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Lead Free Status / Rohs Status: Not Compliant

Burst Address Table (MODE = NC/V
Truth Table
Notes:
3.
4.
5.
6.
7.
8.
9.
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
(external)
Address
A...A00
A...A01
A...A10
A...A11
X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.
Suspending burst generates wait cycle.
For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
First
Operation
[3, 4, 5, 6, 7, 8, 9]
(internal)
Address
Second
A...A01
A...A00
A...A11
A...A10
(internal)
Address
Address Used CE CE
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
A...A10
A...A11
A...A00
A...A01
Third
CC
(internal)
Address
)
Fourth
A...A11
A...A10
A...A01
A...A00
H
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
2
CE
8
H
H
H
H
H
X
L
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
Burst Address Table (MODE = GND)
2
(external)
Address
ADSP ADSC ADV WRITE OE
A...A00
A...A01
A...A10
A...A11
First
X
H
H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
L
L
L
L
L
L
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
(internal)
Address
Second
A...A01
A...A10
A...A11
A...A00
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
(internal)
Address
A...A10
A...A11
A...A00
A...A01
Third
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
(internal)
Address
Fourth
A...A11
A...A00
A...A01
A...A10
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D