CY7C1381C-100BGC Cypress Semiconductor Corp, CY7C1381C-100BGC Datasheet - Page 21

• Manufacturer Part Number: CY7C1381C-100BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381C-100BGC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05238 Rev. *B
Scan Register Sizes
Identification Codes
Identification Register Definitions
REGISTER NAME
Instruction
Bypass
ID
Boundary Scan Order
INSTRUCTION
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
INSTRUCTION FIELD
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
CODE
000
001
010
100
101
011
110
111
DESCRIPTION
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
00000110100
CY7C1381C
(512KX36)
000001
100101
01010
010
1
BIT SIZE(X36)
00000110100
CY7C1383C
(1MX18)
000001
010101
32
72
01010
3
1
010
1
DESCRIPTION
Describes the version number.
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
BIT SIZE(X18)
32
72
3
1
CY7C1381C
CY7C1383C
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