CY7C1381C-117AC Cypress Semiconductor Corp, CY7C1381C-117AC Datasheet
CY7C1381C-117AC
Specifications of CY7C1381C-117AC
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CY7C1381C-117AC Summary of contents
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... TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable Cypress Semiconductor Corporation Document #: 38-05238 Rev. *B Functional Description The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum ) DD glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version) ...
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... Logic Block Diagram – CY7C1381C (512K x 36) ADDRESS A0, A1, A REGISTER MODE ADV CLK COUNTER AND LOGIC CLR ADSC ADSP DQ DQP BYTE BYTE WRITE REGISTER WRITE REGISTER DQ DQP , BYTE WRITE REGISTER ADDRESS A0, A1, A REGISTER DQ , DQP BYTE MODE WRITE REGISTER CE CLK C DQ DQP ...
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... TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ /DNU CY7C1383C DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1381C CY7C1383C DDQ 76 V SSQ DQP SSQ 70 V DDQ ( DDQ V 60 SSQ SSQ V 54 DDQ Page [+] Feedback ...
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... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ Document #: 38-05238 Rev. *B 119-ball BGA (1 Chip Enable with JTAG) CY7C1381C (512K x 36 ADSP ADSC DQP ADV CLK BWE DQP MODE TMS TDI TCK TDO CY7C1383C ( ADSP ADSC ...
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... DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M 288M DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05238 Rev. *B 165-ball fBGA (3 Chip Enable) CY7C1381C (512K x 36 BWE CLK TDI A1 TDO A A0 TCK A TMS ...
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... CY7C1381C–Pin Definitions TQFP BGA (3-Chip (1-Chip Name Enable) Enable 37,36,32,33,34, P4,N4,A2,B2, 35,42,43,44,45, ,R2,A3,B3,C3,T 46,47,48,49,50, 3,T4,A5,B5,C5, 81,82,99,100 T5,A6,B6,C6,R6 93,94,95,96 L5,G5,G3, CLK [ ADV 84 A4 ADSP Document #: 38-05238 Rev. *B fBGA (3-Chip Enable) I/O R6,P6,A2,A10, Input- Address Inputs used to select one of the B2,B10,N6,P3, Synchronous 512K address locations ...
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... CY7C1381C–Pin Definitions (continued) TQFP BGA (3-Chip (1-Chip Name Enable) Enable ADSC 87 M4 BWE 52,53,56,57,58, K6,L6,M6,N6, 59,62,63,68,69, ,L7,N7,P7,E6,F 72,73,74,75,78, 6,G6,H6,D7,E7, 79,2,3,6,7,8,9, G7,H7,D1,E1,G 12,13,18,19,22, 1,H1,E2,F2,G2, 23,24,25,28,29 H2,K1,L1,N1,P1 ,K2,L2,M2,N2 51,80,1,30 P6,D6,D2,P2 DQP [A:D] MODE 15,41,65,91 J2,C4,J4,R4,J6 DD Document #: 38-05238 Rev. *B fBGA (3-Chip Enable) I/O ...
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... CY7C1381C–Pin Definitions (continued) TQFP BGA (3-Chip (1-Chip Name Enable) Enable) V 4,11,20,27, A1,F1,J1,M1,U1 DDQ 54,61,70,77 , A7,F7,J7,M7,U7 V 17,40,67,90 H2,D3,E3,F3,H3 SS ,K3, M3,N3, P3,D5,E5,F5,H5 ,K5, M5,N5,P5 V 5,10,21,26, - SSQ 55,60,71,76 TDO - U5 TDI - U3 TMS - U2 TCK - U4 NC 16,38,39,66 B1,C1,R1,T1,T2 ,J3,D4,L4,J5,R5 ,T6,U6,B7,C7 /DNU Document #: 38-05238 Rev. *B fBGA (3-Chip Enable) ...
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... A9 Input- Advance Input signal, sampled on the Synchronous rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. CY7C1381C CY7C1383C Description [ and CE are feed the 2-bit counter. ...
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... Selects Burst Order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst DD sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. CY7C1381C CY7C1383C Description are [1:0] are [1:0] and DQP ...
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... JTAG feature is not being utilized, this pin can be disconnected or connected to V This pin is not available on TQFP packages. R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to V available on TQFP packages. CY7C1381C CY7C1383C Description This pin is not SS Page ...
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... No Connects. Not internally connected to B4,B11,C1,C2,C the die. 36M, 72M, 144M and 288M are 10,D1,D10,E1,E address expansion pins are not internally 10,F1,F10,G1,G connected to the die. 10,H3,H9,H10,J 2,J11,K2,K11, L2,L11,M2,M11, N2,N5,N7,N10, N11,P1,P2,R2 - Ground/DNU This pin can be connected to Ground or should be left floating. CY7C1381C CY7C1383C Description Page [+] Feedback ...
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... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). C0 The CY7C1381C/CY7C1383C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... ADSC CY7C1381C CY7C1383C Min. Max. Unit CYC 2t ns CYC 2t ns CYC 0 ns ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State Tri-State L L-H Tri-State L L L-H Tri-State L L-H Tri-State . Writes may occur only on subsequent clocks X Page [+] Feedback ...
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... Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current Partial Truth Table for Read/Write Function (CY7C1381C) Read Read Write Byte A (DQ , DQP ) A A Write Byte B(DQ , DQP ) ...
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... Truth Table for Read/Write Function (CY7C1383C) Write All Bytes Document #: 38-05238 Rev. *B BWE CY7C1381C CY7C1383C Page [+] Feedback ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381C/CY7C1383C incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture setup plus hold time (t plus The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a portion of SAMPLE/PRELOAD instruction. If this is an issue still CY7C1381C CY7C1383C Unlike the SAMPLE/PRELOAD Page [+] Feedback ...
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... Do not use these instructions. TAP Timing CYC TL t TMSS t TMSH t TDIS t TDIH t TDOV t TDOX DON’T CARE UNDEFINED [9, 10] Symbol t TCYC TDOV t TDOX t TMSS t TDIS TMSH t TDIH 1ns R F CY7C1381C CY7C1383C 5 6 Min Max Units 100 ns 10 MHz Page [+] Feedback ...
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... OL DDQ 2.5V OL DDQ I = 100 µ 3.3V DDQ 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1381C CY7C1383C V to 2.5V SS 1.25V 20pF O MIN MAX UNITS 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 ...
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... Describes the version number. 01010 01010 Reserved for Internal Use 000001 000001 Defines memory type and architecture 100101 010101 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor Indicates the presence register. BIT SIZE(X36 CY7C1381C CY7C1383C BIT SIZE(X18 Page [+] Feedback ...
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... BGA Boundary Scan Order CY7C1381C (512K x 36) BIT BALL Document #: 38-05238 Rev. *B BIT BALL Not Bonded (Preset Internal Internal CY7C1381C CY7C1383C Page [+] Feedback ...
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... Document #: 38-05238 Rev. *B BIT BALL Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Internal Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Internal 68 Not Bonded (Preset Internal Internal CY7C1381C CY7C1383C Page [+] Feedback ...
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... Boundary Scan Order CY7C1381C (512K x 36) BIT# BALL B10 9 A10 10 C11 11 E10 12 F10 13 G10 14 D10 15 D11 16 E11 17 F11 18 G11 19 H11 20 J10 21 K10 22 L10 23 M10 24 J11 25 K11 26 L11 27 M11 28 N11 29 R11 30 R10 P10 P11 Document #: 38-05238 Rev. *B BIT# BALL ID 37 ...
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... R1 45 Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset CY7C1381C CY7C1383C Page [+] Feedback ...
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... All Speeds DD ≥ V ≤ 0.3V, – 0. /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1381C CY7C1383C Ambient Temperature DDQ 0°C to +70°C 3.3V – 5%/+10% 2.5V – Min. Max. Unit 3.135 3.6 3.135 ...
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... MHz 3.3V 2.5V DDQ R = 317Ω 3.3V V OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2. OUTPUT GND =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1381C CY7C1383C BGA fBGA Package Package Unit °C °C BGA fBGA Package Package Unit ...
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... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1381C CY7C1383C 117 MHz 100 MHz Max. Min. Max. Unit ...
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... Data Out (Q) High-Z t CDV Single READ Document #: 38-05238 Rev ADS t ADH ADVH ADVS ADV suspends burst t CDV t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED CY7C1381C CY7C1383C Deselect Cycle t CHZ Q( Q(A2 Burst wraps around to its initial state Page [+] Feedback ...
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... BURST READ Single WRITE Document #: 38-05238 Rev. *B ADSC extends burst t t WEH WES ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED CY7C1381C CY7C1383C t ADS t ADH A3 t WES t WEH t ADVS t ADVH D(A3 Extended BURST WRITE Page [+] Feedback ...
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... DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05238 Rev WES WEH OELZ D(A3) t CDV Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH LOW. X CY7C1381C CY7C1383C A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs is HIGH LOW HIGH Page [+] Feedback ...
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... I DDZZ ALL INPUTS (except ZZ) Outputs (Q) Ordering Information Speed (MHz) Ordering Code 133 CY7C1381C-133AC CY7C1383C-133AC CY7C1381C-133BGC CY7C1383C-133BGC CY7C1381C-133BZC CY7C1383C-133BZC 117 CY7C1381C-117AC CY7C1383C-117AC CY7C1381C-117BGC CY7C1383C-117BGC CY7C1381C-117BZC CY7C1383C-117BZC CY7C1381C-117AI CY7C1383C-117AI CY7C1381C-117BGI CY7C1383C-117BGI CY7C1381C-117BZI CY7C1383C-117BZI Document #: 38-05238 Rev. *B High-Z DON’T CARE Package Name Part and Package Type A101 100-lead Thin Quad Flat Pack ( ...
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... CY7C1381C-100AC CY7C1383C-100AC CY7C1381C-100BGC CY7C1383C-100BGC CY7C1381C-100BZC CY7C1383C-100BZC CY7C1381C-100AI CY7C1383C-100AI CY7C1381C-100BGI CY7C1383C-100BGI CY7C1381C-100BZI CY7C1383C-100BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 16.00±0.20 14.00±0.10 100 1 ...
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... Package Diagrams (continued) Document #: 38-05238 Rev. *B CY7C1381C CY7C1383C 51-85115-*B Page [+] Feedback ...
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... Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05238 Rev. *B 165-Ball FBGA ( 1.2 mm) BB165A CY7C1381C CY7C1383C 51-85122-*C Page ...
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... Document History Page Document Title: CY7C1381C/CY7C1383C 18-Mb (512K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05238 REV. ECN NO. Issue Date ** 116278 08/27/02 *A 121541 11/21/02 *B 206081 See ECN Document #: 38-05238 Rev. *B Orig. of Change Description of Change SKX New Data Sheet DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122 (BB165A) to rev ...