CY7C1381C-117AC Cypress Semiconductor Corp, CY7C1381C-117AC Datasheet - Page 11

• Manufacturer Part Number: CY7C1381C-117AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381C-117AC

• Density: 18Mb
• Access Time (max): 7.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 117MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 190mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05238 Rev. *B
CY7C1383C:Pin Definitions
V
V
V
V
TDO
TDI
TMS
TCK
DD
DDQ
SS
SSQ
Name
55,60,71,76,
15,41,65,91
54,61,70,77
17,40,67,90
5,10,21,26,
4,11,20,27,
Enable)
(3-Chip
TQFP
-
-
-
-
D3,D5,E3,E5,F3
H5,K3,K5,L3,M3
A1,A7,F1,F7,J1,
C4,J2,J4,J6,R4
J7,M1,M7,U1,U
,F5,G5,H3,
N5,P3,P5
Enable)
(1-Chip
M5,N3,
(continued)
BGA
U5
U3
U2
U4
7
,
-
K6,K7,L5,L6,L7,
H7,J5,J6,J7,K5,
M6,M7,N4,
L9,M3,M9,
G6,G7,H1,
D4,D8,E4,
C3,C9,D3,
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
H2,H5,H6,
H4,H8,J4,
L4,L8,M4,
D9,E3,E9,
F3,F9,G3,
E6,E7,F5,
F6,F7,G5,
E8,F4,F8,
J8,K4,K8,
K3,K9,L3,
G9,J3,J9,
Enable)
(3-Chip
G4,G8,
N3,N9
fBGA
M5,
M8
N8
P7
P5
R5
R7
-
Power Supply Power supply inputs to the core of the
Synchronous
Synchronous
Synchronous
JTAG-Clock
JTAG serial
JTAG serial
JTAG serial
I/O Ground
I/O Power
Ground
Supply
output
input
input
I/O
device.
Power supply for the I/O circuitry.
Ground for the core of the device.
Ground for the I/O circuitry.
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be left floating or connected to V
through a pull up resistor. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be disconnected or connected to V
This pin is not available on TQFP packages.
Clock input to the JTAG circuitry. If the
JTAG feature is not being utilized, this pin
must be connected to V
available on TQFP packages.
Description
CY7C1381C
CY7C1383C
SS
. This pin is not
Page 11 of 36
DD
DD
.
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