CY7C1381C-117AC Cypress Semiconductor Corp, CY7C1381C-117AC Datasheet - Page 9

• Manufacturer Part Number: CY7C1381C-117AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381C-117AC

• Density: 18Mb
• Access Time (max): 7.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 117MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 190mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05238 Rev. *B
CY7C1383C:Pin Definitions
A
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
0
, A
Name
1
2
3
A,
[2]
1
BW
, A
B
80,81,82,99,100
35,42,43,44,45,
46,47,48,49,50,
37,36,32,33,34,
Enable)
(3-Chip
TQFP
93,94
88
87
89
98
97
92
86
83
P4,N4,A2,B2,
C2,R2,T2,A3,
B3,C3,T3,A5,
B5,C5,T5,A6,
B6,C6,R6,T6
Enable)
(1-Chip
L5,G3
BGA
M4
H4
G4
K4
E4
F4
-
-
R8,R9,R10,R11
B10,N6,P3,P4,
A10,A11,B2,
P8,P9,P10,
P11,R3,R4,
R6,P6,A2,
Enable)
(3-Chip
B5,A4
fBGA
B7
A7
B6
A3
B3
A6
B8
A9
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
I/O
Address Inputs used to select one of the
1M address locations. Sampled at the ris-
ing edge of the CLK if ADSP or ADSC is
active LOW, and CE
sampled active. A
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of
CLK.
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device. ADSP is ignored
if CE
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
select/deselect the device.
Output Enable, asynchronous input,
active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE
is masked during the first clock of a read
cycle when emerging from a deselected
state.
Advance Input signal, sampled on the
rising edge of CLK. When asserted, it
automatically increments the address in a
burst cycle.
[A:B]
1
is HIGH.
and BWE).
Description
[1:0]
2
1
1
1
, CE
and CE
and CE
and CE
feed the 2-bit counter.
CY7C1381C
CY7C1383C
2
, and CE
2
3
3
[2]
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