CY7C138-35JC Cypress Semiconductor Corp, CY7C138-35JC Datasheet - Page 7

• Manufacturer Part Number: CY7C138-35JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C138-35JC

• Density: 32Kb
• Access Time (max): 35ns
• Operating Supply Voltage (typ): 5V
• Package Type: LCC
• Operating Temp Range: 0C to 70C
• Supply Current: 160mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Word Size: 8b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06037 Rev. *B
Switching Waveforms
Read Timing with Port-to-Port Delay (M/S = L)
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
Notes:
20. BUSY = HIGH for the writing port.
21. CE
22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
24. R/W must be HIGH during all address transitions.
SEM OR CE
ADDRESS
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
be placed on the bus for the required t
pulse can be as short as the specified t
ADDRESS
DATA OUT
ADDRESS
DATA
DATA
L
DATA IN
= CE
R/W
R/W
OUTL
OE
R
INR
= LOW.
R
R
L
(continued)
t
SD
SA
PWE
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write
.
t
HZOE
[20, 21]
t
MATCH
SCE
MATCH
t
t
HIGH IMPEDANCE
WC
AW
[22, 23, 24]
t
WC
t
PWE
t
PWE
PWE
t
WDD
t
t
VALID
SD
SD
DATA VALID
or (t
HZWE
+ t
t
DDD
SD
) to allow the I/O drivers to turn off and data to
t
HD
t
HD
t
LZOE
t
HA
CY7C138
CY7C139
VALID
Page 7 of 16
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