IMIB9948CA Cypress Semiconductor Corp, IMIB9948CA Datasheet - Page 2

• Manufacturer Part Number: IMIB9948CA
• Manufacturer: Cypress Semiconductor Corp

Specifications of IMIB9948CA

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07079 Rev. *D
Pin Description
Note:
Output Enable/ Disable
The B9948 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are dis-
abled in a LOW state. When SYNC_OE is set HIGH, the out-
puts are enabled as shown in Figure 1.
1.
3
4
2
9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29,
31
1
5
6
10, 14, 18, 22, 26,
30
7
8, 12, 16, 20, 24,
28, 32
SYNC_OE
PD = internal pull-down, PU = internal pull-up.
TCLK
Pin
Q
[[1]]
PECL_CLK
PECL_CLK#
TCLK
Q(11:0)
TCLK_SEL
SYNC_OE
TS#
VDDC
VDD
VSS
Name
VDDC
PWR
Figure 1. SYNC_OE Timing Diagram
I, PU
I, PD
I, PU
I, PU
I, PU
I, PU
I/O
O
PECL Input Clock
PECL Input Clock
External Reference/Test Clock Input
Clock Outputs
Clock Select Input. When LOW, PECL clock is selected and
when HIGH TCLK is selected.
Output Enable Input. When asserted HIGH, the outputs are
enabled and when set LOW the outputs are disabled in a LOW
state.
Three-state Control Input. When asserted LOW, the output
buffers are three-stated. When set HIGH, the output buffers
are enabled.
3.3V Power Supply for Output Clock Buffers
3.3V Power Supply
Common Ground
Description
B9948
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