IS61LV6416-12T ISSI, Integrated Silicon Solution Inc, IS61LV6416-12T Datasheet - Page 10

• Manufacturer Part Number: IS61LV6416-12T
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LV6416-12T

• Density: 1Mb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 100mA
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

IS61LV6416
IS61LV6416L
10
WRITE CYCLE NO. 4
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The
referenced to the rising or falling edge of the signal that terminates the Write.
ADDRESS
UB, LB
D
OUT
WE
D
OE
CE
IN
LOW
DATA UNDEFINED
(LB, UB Controlled, Back-to-Back Write)
t
HZWE
ADDRESS 1
t
SD
t
t
WORD 1
SA
WC
t
PBW
HIGH-Z
DATA
VALID
IN
t
t
HD
HA
t
SA
ADDRESS 2
t
t
(1,3)
SD
WC
WORD 2
t
PBW
DATA
VALID
IN
t
t
LZWE
SA
t
,
Integrated Silicon Solution, Inc.
HD
t
t
HA
HA
,
t
SD
, and
UB_CEWR4.eps
t
HD
timing is
ISSI
11/22/05
Rev. I
®