KM29W040AT Samsung Semiconductor, KM29W040AT Datasheet - Page 2

• Manufacturer Part Number: KM29W040AT
• Manufacturer: Samsung Semiconductor

Specifications of KM29W040AT

• Cell Type: NAND
• Density: 4Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-II
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

512K x 8 Bit NAND Flash Memory
FEATURES
KM29W040AT, KM29W040AIT
PIN CONFIGURATION
- Memory Cell Array : 512K x 8
- Data Register
- Frame Program : 32 Byte in 500 s
- Block Erase : 4K Byte in 6ms
- Random Access : 15 s(Max.)
- Serial Frame Access : 120ns(Min.)
- 10 A Standby Current
- 10mA Read/ Program/Erase Current
- Endurance : 100K Program/Erase Cycles
Voltage Supply: 3.0V~5.5V
Organization
Automatic Program and Erase (Typical)
32-Byte Frame Read Operation
Command/Address/Data Multiplexed I/O port
Low Operation Current (Typical)
Reliable CMOS Floating-Gate Technology
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
NOTE : Connect all V
Do not leave V
VSS
VSS
CLE
ALE
I/O0
I/O1
I/O2
I/O3
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
WE
WP
44(40) TSOP (II)
: 32 x 8 bit
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
CC
CC,
and V
V
SS
SS
or GND inputs disconnected.
pins of each device to common power supply outputs.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
RE
R/B
GND
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
VCC
2
GENERAL DESCRIPTION
The KM29W040A is a 512Kx8bit NAND Flash Memory. Its
NAND cell structure provides the most cost-effective solution
for Digital Audio Recording. A Program operation programs a
32-byte frame in typically 500 s and an Erase operation erase
a 4K-byte block in typically 6ms. Data in a frame can be read
out at a burst cycle rate of 120ns/byte. The I/O pins serve as
the ports for address and data input/output as well as for com-
mand inputs. The on-chip write controller automates the pro-
gram and erase operations, including program or erase pulse
repetition where required, and performs internal verification of
cell data.
The KM29W040A is an optimum solution for flash memory
application that do not require the high performance levels or
capacity of larger density flash memories. These application
include
Devices(TAD) and other consumer applications that require
voice data storage.
PIN DESCRIPTION
I/O
Pin Name
GND
0
CLE
ALE
V
R/B
V
N.C
WE
WP
CE
RE
~ I/O
CC
SS
data
7
storage
Data Inputs/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ground Input
Ready/Busy output
Power
Ground
No Connection
in
FLASH MEMORY
digital
Pin Function
Telephone
Answering