KM29W040AT Samsung Semiconductor, KM29W040AT Datasheet - Page 4

• Manufacturer Part Number: KM29W040AT
• Manufacturer: Samsung Semiconductor

Specifications of KM29W040AT

• Cell Type: NAND
• Density: 4Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-II
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

Table 1. COMMAND SETS
PRODUCT INTRODUCTION
The KM29W040A is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell
arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The
memory array is composed of unit NAND structures in which 8 cells are connected serially.
Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 unit NAND structures of 8bits each. The
array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation
is executed on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks.
The KM29W040A has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades
to higher density flash memories by maintaining consistency in system board design. Command, address and data are all written
through I/O s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one
bus cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space
requires a 19-bit address, low row address and high row address. Frame Read and frame Program require the same three address
cycles following by a command input. In the Block Erase operation, however, only the two row address cycles are required.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29W040A.
KM29W040AT, KM29W040AIT
Read
Reset
Frame Program
Block Erase
Status read
Read ID
Function
1st. Cycle
00h
FFh
80h
60h
70h
90h
2nd. Cycle
10h
D0h
4
-
-
-
-
Acceptable Command during Busy
FLASH MEMORY
O
O