CY2292FZ Cypress Semiconductor Corp, CY2292FZ Datasheet - Page 6

• Manufacturer Part Number: CY2292FZ
• Manufacturer: Cypress Semiconductor Corp
• Type: Programmable PLL Clock Generatorr

Specifications of CY2292FZ

• Number Of Elements: 3
• Supply Current: 100mA
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 30MHz
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 0.076923 to 90MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07449 Rev. *C
Switching Characteristics, Commercial 5.0V
Switching Characteristics, Commercial 3.3V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
9A
9B
9C
9D
10A
10B
1
3
4
5
6
7
8
9A
9B
9C
9D
10A
10B
Parameter
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
Lock Time for CPLL
Lock Time for UPLL and
SPLL
Slew Limits
Output Period
Output Duty
Cycle
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
CPUCLK Slew
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
Lock Time for CPLL Lock Time from Power-up
Lock Time for
UPLL and SPLL
Slew Limits
[11]
Name
Name
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
Clock output range, 3.3V
operation
Duty cycle for outputs, defined as t
f
Duty cycle for outputs, defined as t
f
Output clock rise time
Output clock fall time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs
Frequency transition rate
Peak-to-peak period jitter (t
% of clock period (f
Peak-to-peak period jitter (t
(4 MHz < f
Peak-to-peak period jitter (16 MHz < f
Peak-to-peak period jitter (f
Lock Time from Power-up
CPU PLL Slew Limits
OUT
OUT
Peak-to-peak period jitter (t
min.), % of clock period (f
Peak-to-peak period jitter (t
min.)
(4 MHz < f
Peak-to-peak period jitter (16 MHz < f
50 MHz)
Peak-to-peak period jitter (f
Lock Time from Power-up
Lock Time from Power-up
CPU PLL Slew Limits
> 66 MHz
< 66 MHz
[3, 12, 14]
OUT
OUT
< 16 MHz)
Description
Description
< 16 MHz)
OUT
[13]
[13]
(continued)
< 4 MHz)
9A
9B
OUT
CY2292
CY2292F
CY2292
CY2292F
OUT
CY2292
CY2292F
max. – t
max. – t
OUT
9A
9B
> 50 MHz)
< 4 MHz)
max. – t
max. – t
OUT
2
2
> 50 MHz)
÷ t
÷ t
9A
9B
< 50 MHz)
OUT
1
1
[12]
[12]
min.),
min.)
9A
9B
<
(66.6 MHz)
(80 MHz)
Min.
20
20
Min.
12.5
40%
45%
1.0
15
20
20
<0.25
<400
<250
Typ.
<0.5
<0.7
<25
< 0.25
< 0.25
< 400
< 250
< 0.5
< 0.7
Typ.
50%
50%
< 25
2.5
10
10
3
(76.923 kHz)
(76.923 kHz)
Max.
500
350
100
13000
13000
50
90
Max.
1
60%
55%
1
1
20.0
66.6
500
350
0.5
80
15
15
50
5
4
1
1
1
CY2292
Page 6 of 11
Unit
MHz
MHz
MHz/
MHz
MHz
Unit
ms
ms
ns
ps
ps
%
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
%
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