CY62147DV18LL-70BVI Cypress Semiconductor Corp, CY62147DV18LL-70BVI Datasheet - Page 5

• Manufacturer Part Number: CY62147DV18LL-70BVI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62147DV18LL-70BVI

• Density: 4Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 1.8V
• Address Bus: 18b
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 10mA
• Operating Supply Voltage (min): 1.65V
• Operating Supply Voltage (max): 2.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05343 Rev. *B
Data Retention Waveform
Switching Characteristics Over the Operating Range
wqewqewq
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes:
10. Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
11. At any given temperature and voltage condition, t
12. t
13. The internal Write time of the memory is defined by the overlap of WE, CE = V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
9.
CE or
BHE.BLE
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.
pulse levels of 0 to V
given device.
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
HZOE
Parameter
V
, t
CC
HZCE
[13]
, t
HZBE
, and t
CC(typ.)
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z
BLE / BHE HIGH to HIGH Z
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
, and output loading of the specified I
transitions are measured when the outputs enter a high impedence state.
[9]
Description
V
CC(min)
t
HZCE
CDR
[11]
[11]
[11, 12]
[11, 12]
[11, 12]
[11]
is less than t
[11]
[11, 12]
OL
LZCE
/I
OH
DATA RETENTION MODE
, t
as shown in the “AC Test Loads and Waveforms” section.
HZBE
IL
Min.
is less than t
, BHE and/or BLE = V
55
10
10
10
55
40
40
40
40
25
10
V
5
0
0
0
0
[10.]
DR
> 1.0 V
55 ns
LZBE
, t
Max.
HZOE
55
55
25
16
20
55
55
20
20
IL
. All signals must be ACTIVE to initiate a write and any
is less than t
Min.
70
10
10
10
70
50
50
45
50
30
10
LZOE
V
5
0
0
0
0
CC(min)
, and t
t
R
70 ns
CY62147DV18
HZWE
Max.
is less than t
70
70
35
16
25
70
70
25
25
MoBL2™
Page 5 of 11
CC(typ)
LZWE
Unit
/2, input
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
for any
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