CY7C1354A-200BGC Cypress Semiconductor Corp, CY7C1354A-200BGC Datasheet - Page 21

• Manufacturer Part Number: CY7C1354A-200BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-200BGC

• Density: 9Mb
• Access Time (max): 3.2ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Supply Current: 560mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.47V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05161Rev. *E
Switching Waveforms
Write Timing
Notes:
46. D(A
47. Individual Byte Write signals (BWx) must be valid on all Write and burst-Write cycles. A Write cycle is initiated when WEN signal is sampled LOW when ADV/LD
the burst sequence of the base address A
MODE input.
is sampled LOW. The byte Write information comes in one cycle before the actual data is presented to the SRAM.
BWa#, BWb#
BWa, BWb,
BWc, BWd
ADDRESS
1
ADV/LD#
) represents the first input to the external address A1. D(A
ADV/LD
WEN
CKE#
R/W#
CEN
CLK
CE
OE#
CE#
OE
DQ
[42, 43, 44, 45, 46, 47]
BW(A
A
1
1
)
t
t
t
t
t
t
S
S
S
S
S
S
Pipeline Write
(continued)
BW(A
A
2
2
2
, etc., where address bits A0 and A1 are advancing for the four-word burst in the sequence defined by the state of the
)
t
SD
t
t
t
t
t
t
H
H
H
H
H
H
Pipeline Write
BW(A
D(A
2
1
+1)
)
t
HD
2
t
) represents the first input to the external address A
KC
t
KL
BW(A
D(A
2
2
+2)
)
BW(A
D(A
2
2
+3)
+1)
t
KH
(CKE# HIGH , eliminates
current L-H clock edge)
Burst Pipeline Write
2
; D(A
BW(A
D(A
2
+2)
2
2
)
+ 1) represents the next input data in
D(A
CY7C1354A
CY7C1356A
2
(Burst Wraps around
+3)
to initial state)
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D(A
2
)