CY7C1354A-200BGC Cypress Semiconductor Corp, CY7C1354A-200BGC Datasheet - Page 5

• Manufacturer Part Number: CY7C1354A-200BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-200BGC

• Density: 9Mb
• Access Time (max): 3.2ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Supply Current: 560mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.47V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05161Rev. *E
Pin Descriptions—256K × 36
82, 83, 99, 100
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 81,
TQFP Pins
256K × 36
98, 92
37,
36,
93,
94,
95,
96
87
88
89
97
86
85
31
64
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 4G, 2R,
6R, 3T, 4T, 5T
PBGA Pins
256K × 36
4E, 6B
4M
4N
5G
3G
4H
3R
4P
4K
2B
4F
4B
7T
5L
3L
Name
BWa,
BWb,
BWc,
WEN
ADV/
MOD
BWd
CEN
CLK
CE
CE
Pin
CE,
A0,
A1,
OE
LD
ZZ
A
E
3
2
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Type
Input
Synchronous Address Inputs: The address register is triggered by a
combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and
true chip enables. A0 and A1 are the two least significant bits (LSBs) of
the address field and set the internal burst counter if burst cycle is
initiated.
Synchronous Byte Write Enables: Each nine-bit byte has its own
active LOW byte Write enable. On load Write cycles (when WEN and
ADV/LD are sampled LOW), the appropriate byte Write signal (BWx)
must be valid. The byte Write signal must also be valid on each cycle of
a burst Write. Byte Write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device two
cycles later. BWa controls DQa pins; BWb controls DQb pins; BWc
controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW if
always doing Writes to the entire 36-bit word.
Synchronous Clock Enable Input: When CEN is sampled HIGH, all
other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
Read Write: WEN signal is a synchronous input that identifies whether
the current loaded cycle and the subsequent burst cycles initiated by
ADV/LD is a Read or Write operation. The data bus activity for the
current cycle takes place two clock cycles later.
Clock: This is the clock input to CY7C1354A. Except for OE, ZZ and
MODE, all timing references for the device are made with respect to the
rising edge of CLK.
Synchronous Active LOW Chip Enable: CE and CE
CE
sampled LOW, along with ADV/LD LOW at the rising edge of clock,
initiates a deselect cycle. The data bus will be High-Z two clock cycles
after chip deselect is initiated.
Synchronous Active High Chip Enable: CE
to enable the chip. CE
to CE and CE
Asynchronous Output Enable: OE must be LOW to Read data. When
OE is HIGH, the I/O pins are in high-impedance state. OE does not need
to be actively controlled for Read and Write cycles. In normal operation,
OE can be tied LOW.
Advance/Load: ADV/LD is a synchronous input that is used to load the
internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected. When
ADV/LD is sampled HIGH, then the internal burst counter is advanced
for any burst that was in progress. The external addresses and WEN
are ignored when ADV/LD is sampled HIGH.
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst sequence
is selected. MODE is a static DC input.
Sleep Enable: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has to be
either LOW or NC.
2
to enable the CY7C1354A. CE or CE
3
.
2
has inverted polarity but otherwise is identical
Pin Description
3
sampled HIGH or CE
2
is used with CE and CE
CY7C1354A
CY7C1356A
3
are used with
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