CY7C68013-128AXC Cypress Semiconductor Corp, CY7C68013-128AXC Datasheet - Page 20

• Manufacturer Part Number: CY7C68013-128AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-128AXC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Compliant

Table 4-1. FX2 Pin Descriptions (continued)
Document #: 38-08012 Rev. *F
TQFP
128
110
112
113
114
115
111
4
5
6
7
8
9
TQFP
100
88
89
90
91
92
93
3
4
5
6
7
8
SSOP
56
8
9
QFN
56
1
2
PE2 or
T2OUT
PE3 or
RXD0OUT
PE4 or
RXD1OUT
PE5 or
INT6
PE6 or
T2EX
PE7 or
GPIFADR8
RDY0 or
SLRD
RDY1 or
SLWR
RDY2
RDY3
RDY4
RDY5
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input
Input
Input
Input
Input
Input
[5]
Default
(PE2)
(PE3)
(PE4)
(PE5)
(PE6)
(PE7)
N/A
N/A
N/A
N/A
N/A
N/A
I
I
I
I
I
I
Multiplexed pin whose function is selected by the PORTECFG.2
bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2.
T2OUT is active (HIGH) for one clock cycle when Timer/Counter
2 overflows.
Multiplexed pin whose function is selected by the PORTECFG.3
bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in Mode 0, this pin provides
the output data for UART0 only when it is in sync mode. Otherwise
it is a 1.
Multiplexed pin whose function is selected by the PORTECFG.4
bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When
RXD1OUT is selected and UART1 is in Mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In Modes
1, 2, and 3, this pin is HIGH.
Multiplexed pin whose function is selected by the PORTECFG.5
bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT5 interrupt request input signal. The INT6 pin
is edge-sensitive, active HIGH.
Multiplexed pin whose function is selected by the PORTECFG.6
bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-high input signal to the 8051 Timer2. T2EX
reloads timer 2 on its falling edge. T2EX is active only if the EXEN2
bit is set in T2CON.
Multiplexed pin whose function is selected by the PORTECFG.7
bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPOLAR.3) for the slave FIFOs connected to FDI[7..0] or
FDI[15..0].
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPOLAR.2) for the slave FIFOs connected to FDI[7..0] or
FDI[15..0].
RDY2 is a GPIF input signal.
RDY3 is a GPIF input signal.
RDY4 is a GPIF input signal.
RDY5 is a GPIF input signal.
Description
CY7C68013
Page 20 of 48