CY7C68013-56LFC Cypress Semiconductor Corp, CY7C68013-56LFC Datasheet - Page 37

• Manufacturer Part Number: CY7C68013-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Not Compliant

Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
There is no specific timing requirement that needs to be met
for asserting PKTEND pin with regards to asserting SLWR.
PKTEND can be asserted with the last data value clocked into
the FIFOs or thereafter. The only consideration is the set-up
time t
Although there are no specific timing requirement for the
PKTEND assertion, there is a specific corner case condition
that needs attention while using the PKTEND to commit a one
byte/word packet. There is an additional timing requirement
that need to be met when the FIFO is configured to operate in
auto mode and it is desired to send two packets back to back:
a full packet (full defined as the number of bytes in the FIFO
meeting the level set in AUTOINLEN register) committed
automatically followed by a short one byte/word packet
committed manually using the PKTEND pin. In this particular
scenario, user must make sure to assert PKTEND at least one
Document #: 38-08012 Rev. *F
t
t
t
t
PKTEND
FIFOADR
IFCLK
SPE
PEH
XFLG
IFCLK
SLWR
DATA
Parameter
SPE
and the hold time t
Figure 9-10. Slave FIFO Synchronous Write Sequence and Timing Diagram
IFCLK Period
PKTEND to Clock Set-up Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
t
SFA
PEH
t
IFCLK
>= t
t
SFD
must be met.
SWR
X-4
t
FDH
Description
t
SFD
X-3
t
FDH
t
SFD
X-2
t
FDH
clock cycle after the rising edge that caused the last byte/word
to be clocked into the previous auto committed packet.
Figure 9-10 below shows this scenario. X is the value the
AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 9-10 shows a scenario where two packets are being
committed. The first packet gets committed automatically
when the number of bytes in the FIFO reaches X (value set in
AUTOINLEN register) and the second one byte/word short
packet being committed manually using PKTEND. Note that
there is at least one IFCLK cycle timing between the assertion
of PKTEND and clocking of the last byte of the previous packet
(causing the packet to be committed automatically). Failing to
adhere to this timing, will result in the FX2 failing to send the
one byte/word short packet.
t
SFD
X-1
t
FDH
20.83
Min.
8.6
2.5
t
SFD
X
t
FDH
At least one IFCLK cycle
t
SFD
Max.
13.5
200
1
>= t
t
FDH
WRH
[15]
CY7C68013
t
t
FAH
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SPE
Unit
ns
ns
ns
ns
t
PEH