CY7C68013-56LFC Cypress Semiconductor Corp, CY7C68013-56LFC Datasheet - Page 41

• Manufacturer Part Number: CY7C68013-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Not Compliant

9.16.2
The Figure 9-18 shows the timing relationship of the SLAVE
FIFO signals during a synchronous write using IFCLK as the
synchronizing clock. The diagram illustrates a single write
followed by burst write of three bytes and committing all four
bytes as a short packet using the PKTEND pin.
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Note: For the burst mode, SLWR and SLCS are left asserted
for the entire duration of writing all the required data values. In
this burst write mode, once the SLWR is asserted, the data on
the FIFO data bus is written to the FIFO on every rising edge
Document #: 38-08012 Rev. *F
PKTEND
FLAGS
FIFOADR
• At t = 0 the FIFO address is stable and the signal SLCS is
• At t = 1, the external master/peripheral must outputs the
• At t = 2, SLWR is asserted. The SLWR must meet the setup
• While the SLWR is asserted, data is written to the FIFO and
IFCLK
SLWR
SLCS
DATA
asserted. (SLCS may be tied low in some applications)
Note: t
is running at 48 MHz, the FIFO address setup time is more
than one IFCLK cycle.
data value onto the data bus with a minimum set up time of
t
time of t
rising edge of IFCLK) and maintain a minimum hold time of
t
SLWR signal). If SLCS signal is used, it must be asserted
with SLWR or before SLWR is asserted. (i.e., the SLCS and
SLWR signals must both be asserted to start a valid write
condition).
on the rising edge of the IFCLK, the FIFO pointer is incre-
mented. The FIFO flag will also be updated after a delay of
t
SFD
WRH
XFLG
before the rising edge of IFCLK.
(time from the IFCLK edge to the deassertion of the
Single and Burst Synchronous Write
from the rising edge of the clock.
SFA
SWR
has a minimum of 25 ns. This means when IFCLK
(time from asserting the SLWR signal to the
t=0
Figure 9-18. Slave FIFO Synchronous Write Sequence and Timing Diagram
t
SFA
t=1
t=2
t
t
SFD
SWR
t
N
IFCLK
t=3
t
FDH
t
WRH
t
XFLG
t
FAH
T=0
t
SFA
of IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 9-18, once the four bytes are written to the
FIFO, SLWR is de-asserted. The short 4-byte packet can be
committed to the host by asserting the PKTEND signal.
There is no specific timing requirement that needs to be met
for asserting PKTEND signal with regards to asserting the
SLWR signal. PKTEND can be asserted with the last data
value or thereafter. The only requirement is that the set-up time
t
Figure 9-18, the number of data values committed includes the
last value written to the FIFO. In this example, both the data
value and the PKTEND signal are clocked on the same rising
edge of IFCLK. PKTEND can also be asserted in subsequent
clock cycles. The FIFOADDR lines should be held constant
during the PKTEND assertion.
Although there is no specific timing requirement for the
PKTEND assertion, there is a specific corner case condition
that needs attention while using the PKTEND to commit a one
byte/word packet. Additional timing requirements exists when
the FIFO is configured to operate in auto mode and it is desired
to send two packets: a full packet (full defined as the number
of bytes in the FIFO meeting the level set in AUTOINLEN
register) committed automatically followed by a short one
byte/word packet committed manually using the PKTEND pin.
In this case, the external master must make sure to assert the
PKTEND pin at least one clock cycle after the rising edge that
caused the last byte/word to be clocked into the previous auto
committed packet (the packet with the number of bytes equal
to what is set in the AUTOINLEN register). Refer to Figure 9-
10 for further details on this timing.
SPE
T=1
T=2
and the hold time t
>= t
t
SFD
SWR
N+1
t
FDH
T=3
t
SFD
N+2
t
PEH
FDH
T=4
must be met. In the scenario of
t
SFD
t
N+3
SPE
[13]
>= t
t
t
XFLG
FDH
T=5
t
WRH
PEH
CY7C68013
t
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