CY7C68013-56LFXC Cypress Semiconductor Corp, CY7C68013-56LFXC Datasheet - Page 43

• Manufacturer Part Number: CY7C68013-56LFXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFXC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Compliant

9.16.4
Figure 9-21 diagrams the timing relationship of the SLAVE
FIFO write in an asynchronous mode. The diagram shows a
single write followed by a burst write of three bytes and
committing the 4-byte-short packet using PKTEND.
Document #: 38-08012 Rev. *F
FIFOADR
PKTEND
• At t = 0 the FIFO address is applied, insuring that it meets
• At t = 1 SLWR is asserted. SLWR must meet the minimum
• At t = 2, data must be present on the bus t
• At t = 3, deasserting SLWR will cause the data to be written
FLAGS
the setup time of t
asserted (SLCS may be tied low in some applications).
active pulse of t
of t
SLWR or before SLWR is asserted.
deasserting edge of SLWR.
from the data bus to the FIFO and then increments the FIFO
pointer. The FIFO flag is also updated after t
deasserting edge of SLWR.
SLWR
DATA
SLCS
WRpwh
Sequence Diagram of a Single and Burst Asynchronous Write
. If the SLCS is used, it must be in asserted with
t=0
t
SFA
WRpwl
t =1
SFA
t
WRpwl
t=2
Figure 9-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram
t
SFD
. If SLCS is used, it must also be
and minimum de-active pulse width
t=3
N
t
t
FDH
WRpwh
t
FAH
t
XFLG
T=0
SFD
t
SFA
XFLG
T=1
before the
t
WRpwl
T=2
from the
t
SFD
T=3
t
N+1
FDH
t
WRpwh
T=4
The same sequence of events is shown for a burst write and
is indicated by the timing marks of T = 0 through 5. Note: In
the burst write mode, once SLWR is deasserted, the data is
written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incre-
mented.
In Figure 9-21 once the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet can be
committed to the host using the PKTEND. The external device
should be designed to not assert SLWR and the PKTEND
signal at the same time. It should be designed to assert the
PKTEND after SLWR is deasserted and met the minimum de-
asserted pulse width. The FIFOADDR lines are to be held
constant during the PKTEND assertion.
t
WRpwl
T=5
t
SFD
T=6
t
N+2
FDH
t
WRpwh
T=7
t
WRpwl
T=8
t
SFD
T=9
t
t
N+3
WRpwh
FDH
t
PEpwl
[13]
CY7C68013
t
XFLG
t
PEpwh
t
FAH
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