CY7C68013-56LFXC Cypress Semiconductor Corp, CY7C68013-56LFXC Datasheet - Page 47

• Manufacturer Part Number: CY7C68013-56LFXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFXC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Compliant

12.0
The following recommendations should be followed to ensure
reliable high-performance operation.
13.0
Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good
Note:
Purchase of I
I
as defined by Philips. EZ-USB FX2 and ReNumeration are trademarks, and EZ-USB is a registered trademark, of Cypress
Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-08012 Rev. *F
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
17. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High
2
• At least a four-layer impedance controlled boards are re-
• Specify impedance targets (ask your board vendor what
• To control impedance, maintain trace widths and trace spac-
• Minimize stubs to minimize reflected signals.
• Connections between the USB connector shell and signal
• Bypass/flyback caps on VBus, near connector, are recom-
• DPLUS and DMINUS trace lengths should be kept to within
• Maintain a solid ground plane under the DPLUS and DMI-
• It is preferred is to have no vias placed on the DPLUS or
• Isolate the DPLUS and DMINUS traces from all other signal
C Patent Rights to use these components in an I
quired to maintain signal quality.
they can achieve).
ing.
ground must be done near the USB connector.
mended.
two mm of each other in length, with preferred length of 20-
30 mm.
NUS traces. Do not allow the plane to be split under these
traces.
DMINUS trace routing.
traces by no less than 10 mm.
Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.
Figure 13-2. Plot of the Solder Mask (White Area)
PCB Layout Recommendations
Quad Flat Package No Leads (QFN)
2
C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips
Via hole for thermally connecting the
QFN to the circuit board ground plane.
Figure 13-1. Cross-section of the Area Underneath the QFN Package
PCB Material
2
Cu Fill
C system, provided that the system conforms to the I
[17]
Solder Mask
0.013” dia
0.017” dia
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package.
Heat is transferred from the FX2 through the device’s metal
paddle on the bottom side of the package. Heat from here, is
conducted to the PCB at the thermal pad. It is then conducted
from the thermal pad to the PCB inner ground plane by a 5 x
5 array of via. A via is a plated through hole in the PCB with a
finished diameter of 13 mil. The QFN’s metal die paddle must
be soldered to the PCB’s thermal pad. Solder mask is placed
on the board top side over each via to resist solder flow into
the via. The mask on the top side also minimizes outgassing
during the solder reflow process.
For further information on this package design please refer to
the application note “Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology.” This application note
can be downloaded from AMKOR’s website from the following
URL:
“www.amkor.com/products/notes_papers/MLF_AppNote_090
2.pdf”. The application note provides detailed information on
board mounting guidelines, soldering flow, rework process,
etc.
Figure 13-1 below display a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that “No Clean”, type 3
solder paste is used for mounting the part. Nitrogen purge is
recommended during reflow.
Figure 13-2 is a plot of the solder mask pattern and Figure 13-
3 displays an X-Ray image of the assembly (darker areas
indicate solder.).
This figure only shows the top three layers of the circuit board:
Top Solder, PCB Dielectric, and the Ground Plane
Cu Fill
Figure 13-3. X-ray Image of the Assembly
PCB Material
2
C Standard Specification
CY7C68013
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