CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 117

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 12-2. Required Idle Cycles Between Commands
13.0
13.1
The proper power-up sequence is required to correctly initialize the Cypress NSEs before functional access to the device can
begin. RST_L and TRST_L should be held low before the power supplies ramp-up. RST_L must be set low for a duration of time
afterward and then set high. The following steps describe the proper power-up sequence.
Figure 13-1 illustrates the proper sequences of the power-up operation.
Notes:
Document #: 38-02041 Rev. *F
3. Set RST_L and TRST_L low.
4. Power up V
5. Hold RST_L low for a minimum of 64 CLK2X cycles. The counting starts on the first rising edge of CLK2X when PHS_L is
7.
8.
applied is not critical.
high, after both V
sequence. For JTAG reset, TRST_L can be brought high after both V
x68/x136 = 1 Cycle
x72/x144 = 1 Cycle
When the register being read is SSR/SRR and it matches the target location of the previous search, a READ operation cannot be issued for 2+TLSZ idle cycles
to avoid reading the old value. Otherwise there is no idle cycle requirement.
The SRAM operation needs to insert idle cycles to avoid SADR bus contention with previous SEARCH.
x272 = 2 Cycles
# of Cycles
Proper Power-up Sequence
2 Cycles
Power
1 Cycle
1 Cycle
1 Cycle
DD
, V
DD
DDQ
and V
PHS_L
and start running CLK2X and PHS_L. The order in which these signals (including V
CLK2x
OPERATIONS
SRAM WRITE
SRAM READ
TRST_L
VDDQ
RST_L
VDD
DDQ
SEARCH
LEARN
WRITE
READ
have reached their steady state voltages. Set RST_L high afterward to complete the power-up
5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT
Figure 13-1. Power-up Sequence
SEARCH
No Wait
5
1
1
2
No Wait /
(TLSZ +
READ
HLAT)
5
1
1
2
64 CLK2x
cycles
[7]
DD
and V
No Wait
WRITE
DDQ
5
1
1
2
have reached their steady state voltages.
No Wait
LEARN
5
1
1
2
CYNSE70064A
DD
TLSZ /(TLSZ
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+ HLAT)
and V
SRAM
5
1
1
2
DDQ
[8]
) are