CYNSE70064A-83BGC Cypress Semiconductor Corp, CYNSE70064A-83BGC Datasheet
CYNSE70064A-83BGC
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... CYNSE70064A Network Search Engine Cypress Semiconductor Corporation Document #: 38-02041 Rev. *F • 3901 North First Street • CYNSE70064A , San Jose CA 95134 • 408-943-2600 Revised November 9, 2004 ...
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... Search on Tables Configured as ×136 Using CYNSE70064A Devices ..... 55 10.12 272-bit Search on Tables Configured as û272 Using a Single CYNSE70064A Device ....... 70 10.13 272-bit Search on Tables x272-configured Using up to Eight CYNSE70064A Devices ....... 72 10.14 272-bit Search on Tables Configured as ×272 Using CYNSE70064A Devices ..... 77 10.15 Mixed-Sized Searches on Tables Configured with Different Widths Using an CYNSE70064A Device ................................................................................................................................................... 92 10 ...
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... Proper Power-up Sequence .................................................................................................. 117 14.0 APPLICATION ........................................................................................................................... 118 15.0 JTAG (1149.1) TESTING ........................................................................................................... 118 16.0 ELECTRICAL SPECIFICATIONS .............................................................................................. 119 17.0 AC TIMING WAVEFORMS ........................................................................................................ 120 18.0 PINOUT DESCRIPTIONS AND PACKAGE DIAGRAMS .......................................................... 122 19.0 ORDERING INFORMATION ...................................................................................................... 126 20.0 PACKAGE DIAGRAM ................................................................................................................ 127 Document #: 38-02041 Rev. *F CYNSE70064A Page 3 of 128 ...
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... Figure 7-2. Addressing the Global Masks Register Array...................................................................... 14 Figure 8-1. CYNSE70064A Database WIDTH Configuration ................................................................ 17 Figure 8-2. Multiwidth Database Configurations Example ..................................................................... 18 Figure 9-1. Addressing of the CYNSE70064A Data and Mask Arrays .................................................. 18 Figure 10-1. Single-Location Read Cycle Timing .................................................................................. 20 Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ....................................................... 21 Figure 10-3 ...
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... Figure 12-5. Table of 31 Devices Made of Four Blocks....................................................................... 107 Figure 12-6. SRAM Read Through Device Number Bank of 31 Devices (Device Number 0 Timing)................................................................................................................... 108 Figure 12-7. SRAM Read Through Device Number 0 in Bank of 31 Devices (Device Number 30 Timing)................................................................................................................. 109 Document #: 38-02041 Rev. *F LIST OF FIGURES (continued) CYNSE70064A Page 5 of 128 ...
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... Figure 12-12. Table of 31 Devices (Four Blocks) ................................................................................ 114 Figure 12-13. SRAM Write Through Device Number 0 in Bank of 31 Devices (Device 0 Timing) ...... 115 Figure 12-14. SRAM Write Through Device Number 0 in Bank of 31 CYNSE70064A Devices (Device Number 30 Timing)................................................................................................................. 116 Figure 13-1. Power-up Sequence........................................................................................................ 117 Figure 14-1 ...
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... Table 12-1. SRAM Bus Address ......................................................................................................... 102 Table 12-2. Required Idle Cycles Between Commands ..................................................................... 117 Table 15-1. Supported Operations ..................................................................................................... 118 Table 16-1. DC Electrical Characteristics for CYNSE70064A ............................................................ 119 Table 16-2. Operating Conditions for CYNSE70064A ........................................................................ 119 Table 15-2. TAP Device ID Register .................................................................................................. 119 Table 17-1. AC Timing Parameters with CLK2X ................................................................................ 120 Document #: 38-02041 Rev ...
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... Table 17-2. 2.5V AC Table for Test Condition of CYNSE70064A ...................................................... 120 Table 18-1. Pinout Descriptions for Pinout Diagram ........................................................................... 123 Table 19-1. Ordering Information ........................................................................................................ 126 Document #: 38-02041 Rev. *F LIST OF TABLES (continued) CYNSE70064A Page 8 of 128 ...
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... Associative Processing Technology™ (APT) and is designed high-performance, pipelined, synchronous, 32K-entry NSE. The CYNSE70064A database entry size can be 68 bits, 136 bits, or 272 bits. In the 68-bit entry mode, the size of the database is 32K entries. In the 136-bit mode, the size of the database is 16K entries, and in the 272-bit mode, the size of the database is 8K entries ...
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... Data Array Configurable as 32K × 68 16K × 136 8K × 272 Mask Array LHI[6:0] Arbitration BHI[2:0] Logic FULL FULO[1:0] CYNSE70064A TAP TAP Controller SADR[21:0] OE_L Pipeline and WE_L SRAM Control CE_L ALE_L LHO[1:0] BHO[2:0] SSF ...
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... Parameter Type Clocks and Reset CLK2X I Master Clock. CYNSE70064A samples all the data and control pins on the positive edge of CLK2X. All signals are driven out of the device on the rising edge of CLK2X (when PHS_L is LOW). PHS_L I Phase. This signal runs at half the frequency of CLK2X and generates an internal CLK CLK2X. See Section 6.0, “ ...
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... LRAM bit set). ALE_L T Address Latch Enable. When this signal is LOW, the addresses are valid on the SRAM address bus database of multiple CYNSE70064As, the ALE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. Cascade Interface LHI[6:0] I Local Hit In ...
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... CYNSE70064A receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X and generate an internal CLK, as shown in Figure 6-1. The CYNSE70064A uses CLK for internal operations. Also noted on these figures are cycles A and cycle B. Cycle A ends on the rising edge of CLK2X, when PHS_L is high. Cycle B ends on the rising edge of the CLK2X when PHS_L is low ...
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... Search operation. 0 Reserved. 0 Valid. During Search operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to 1. This bit updates only when the device is a global winner in a Search operation. 0 Reserved. CYNSE70064A Description ...
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... Last Device on the SRAM Bus. When set, this device is the last device on the SRAM bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L signals. In cycles where no CYNSE70064A device in a depth-cascaded table drives these signals, this devices drives the signals as follows: SADR = 22’h3FFFFF, CE_L = 1, WE_L = 1, and ALE_L = 1 ...
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... This field may change in future. Document #: 38-02041 Rev. *F [5] Revision Number. This is the current device revision number. Numbers start at one and increment by one for each revision of the device. This is the CYNSE70064A implementation number. 0 Reserved. This is the device identification number. Reserved. 000 These are the three MSBs of the device identification number ...
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... NSE Architecture and Operation Overview The CYNSE70064A consists of 32K × 68-bit storage cells referred to as data bits. There is a mask cell corresponding to each data cell. Figure 8-1 shows the three organizations of the device based on the value of the CFG bits in the command register. ...
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... The CYNSE70064A device can be configured to contain tables of different widths, even within the same chip. Figure 8-2 shows a sample configuration of different widths. Figure 8-2. Multiwidth Database Configurations Example 9.0 Data and Mask Addressing Figure 9-1 shows CYNSE70064A data and mask array addressing. ...
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... Table 10-4 and Table 10-5. The host ASIC selects the CYNSE70064A for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70064A with the LDEV bit set. The host ASIC also supplies SADR[21:20] on CMD[8:7] in cycle A of the Read instruction if the Read is directed to the external SRAM. ...
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... SSR[1] | DQ[1], SSR[0] | DQ[0]}. ID 10: Reserved If DQ[29 this field carries the address of the SRAM External location. If DQ[29 the SSRI specified on DQ[28:26] SRAM is used to generate the address of the SRAM location: {SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]} DQ[20:19] 11: Register CYNSE70064A cycle cycle cycle Data DQ[14:0] [6] [6] ...
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... Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[ using CMDV = 1 and the address supplied on the DQ bus, as shown in Table 10-6. The host ASIC selects the CYNSE70064A where ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70064A with the LDEV bit set. ...
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... External Reserved If DQ[29 this field carries the address of the SRAM SRAM location. If DQ[29 the SSR specified on DQ[28:26] is used to generate the address of SRAM location: {SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}. DQ[20:19] 11: Register CYNSE70064A cycle 3 cycle 4 X DQ[14:0] DQ[18:6] DQ[5:0] Reserved Register address Page 22 of 128 ...
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... ADR field of the WBURREG register) of the selected device. The CYNSE70064A writes the data on the DQ[67:0] bus only to the subfield that has the corresponding mask bit set the GMR specified by the index CMD[5:3] supplied in cycle 1. The CYNSE70064A drives the EOT signal LOW from cycle 3 to cycle n ...
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... Search on tables configured as ×272 using one device • 272-bit Search on tables configured as ×272 using up to eight devices • 272-bit Search on tables configured as ×272 using devices • Mixed-size searches on tables configured with different widths using an CYNSE70064A. 10.6 68-bit Search on Tables Configured as ×68 using a Single CYNSE70064A Device Figure 10-6 shows the timing diagram for a Search command in the 68-bit-configured table (CFG = 00000000) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1 ...
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... L is the winning address that is driven as part of the SRAM address on the SADR[21:0] lines (See “SRAM Addressing” on page 101.) Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 Search1 Search3 Search2 Hit Miss Hit x 68 Table (One Device) CYNSE70064A cycle cycle cycle Search4 Miss Page 25 of 128 ...
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... Search on Tables Configured as ×68 Using up to Eight CYNSE70064A Devices The hardware diagram of the Search subsystem of eight devices is shown in Figure 10-8. The following are the parameters programmed into the eight devices. • First seven devices (devices 0–6): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. ...
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... Figure 10-8. Hardware Diagram for a Table With Eight Devices Document #: 38-02041 Rev Hit Miss Miss Hit Miss Miss Miss Miss 6 5 CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[ CYNSE70064A # CYNSE70064A #4 LHO[ LHI LHI CYNSE70064A #5 LHO[ LHI LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 CYNSE70064A 3 Hit Hit Miss Hit SRAM LHI LHO[ ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-9. Timing Diagram for 68-bit Search Device Number 0 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (This (This device device ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-10. Timing Diagram for 68-bit Search Device Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Local on this winner device. ) but not global winner.) ...
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... SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be compared. Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Local on this winner device ...
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... K 67 Location address 262143 CFG = 00000000 (68-bit configuration) Figure 10-12. x68 Table with Eight Devices Max Table Size 32K × 68 bits 256K × 68 bits 992K × 68 bits Number of CLK Cycles CYNSE70064A 0 0 (First matching entry) Latency in CLK Cycles Page 31 of 128 ...
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... The hardware diagram of the Search subsystem of 31 devices is shown in Figure 10-13. Each of the four blocks in the diagram represents eight CYNSE70064A devices (except the last, which has seven devices). The diagram for a block of eight devices is shown in Figure 10-14. The following are the parameters programmed into the 31 devices. ...
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... BHI[2] BHI[1] Block of 8 CYNSE70064As Block 1 (Devices 8–15) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70064As Block 2 (Devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70064As Block 3 (Devices 24–30) BHO[2] BHO[1] CYNSE70064A BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] 3 Figure 10-14. Hardware Diagram for a Block Eight Devices Document #: 38-02041 Rev CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[ CYNSE70064A # CYNSE70064A #4 LHO[ LHI LHI CYNSE70064A #5 LHO[ LHI LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 CYNSE70064A LHI LHO[ LHI LHO[ LHI ...
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... Figure 10-15. Timing Diagram for Each Device In Block Number 0 (Miss on Each Device) Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 35 of 128 ...
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... Figure 10-16. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 36 of 128 ...
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... Figure 10-17. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (This on device this global device.) winner) Search2 Search4 (Miss (Miss ...
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... Figure 10-18. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 38 of 128 ...
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... Figure 10-19. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 39 of 128 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-20. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Hit on but this not device.) winner ...
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... Figure 10-21. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on this on this device.) device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 41 of 128 ...
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... Figure 10-22. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 42 of 128 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-23. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Global (Miss on winner .) this device.) Search4 Search2 (Hit ...
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... Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 (Except the Last Device [Device 30]) CYNSE70064A cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search4 Search2 (Miss on (Miss on this device.) this device.) Page 44 of 128 ...
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... Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Hit on (Hit on some some device device above.) above ...
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... Location address 1015807 CFG = 00000000 devices (68-bit configuration) × Figure 10-26. 68 Table with 31 Devices Max Table Size 32K × 68 bits 256K × 68 bits 996K × 68 bits Number of CLK Cycles CYNSE70064A 0 GMR K 0 (First matching entry) Latency in CLK Cycles Page 46 of 128 ...
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... Search on Tables Configured as ×136 Using a Single CYNSE70064A Device Figure 10-27 shows the timing diagram for a Search command in the 136-bit-configured table (CFG = 01010101) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this Search subsystem is shown in Figure 10-28 ...
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... L 32766 CFG = 01010101 (136-bit configuration) × Figure 10-29. 136 Table with One Device Max Table Size 16K × 136 bits 128K × 136 bits 496K × 136 bits Number of CLK Cycles CYNSE70064A 0 0 (First matching entry) Latency in CLK Cycles Page 48 of 128 ...
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... Search on Tables Configured as ×136 Using up to Eight CYNSE70064A Devices The hardware diagram of the Search subsystem of eight devices is shown in Figure 10-30. The following are parameters programmed into the eight devices. • First seven devices (devices 0–6): CFG = 01010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 10-30. Hardware Diagram for a Table with Eight Devices Document #: 38-02041 Rev CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[ CYNSE70064A #3 LHO[ CYNSE70064A # LHI LHI CYNSE70064A #5 LHO[ LHI LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 CYNSE70064A LHI LHO[ LHI ...
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... Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-31. Timing Diagram for 136-bit Search Device Number 0 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle cycle cycle Search1 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-32. Timing Diagram for 136-bit Search Device Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Local on this but not device.) global winner.) Search4 Search2 ...
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... SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0]) compared against all odd locations. Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Local on this but not device.) global winner.) ...
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... B L 262142 CFG = 01010101 devices (136-bit configuration) Figure 10-34. ×136 Table with Eight Devices Max Table Size 16K × 136 bits 128K × 136 bits 496K × 136 bits Number of CLK Cycles CYNSE70064A 0 Odd B 0 (First matching entry) Latency in CLK Cycles ...
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... The hardware diagram of the Search subsystem of 31 devices is shown in Figure 10-35. Each of the four blocks in the diagram represents a block of eight CYNSE70064A devices (except the last, which has seven devices). The diagram for a block of eight devices is shown in Figure 10-36. Following are the parameters programmed into the 31 devices. ...
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... BHI[2] BHI[1] Block of 8 CYNSE70064As Block 1 (devices 8–15) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70064As Block 2 (devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70064As Block 3 (devices 24–30) BHO[2] BHO[1] CYNSE70064A BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] 3 Figure 10-36. Hardware Diagram for a Block Eight Devices Document #: 38-02041 Rev CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[ CYNSE70064A # CYNSE70064A #4 LHO[ LHI LHI CYNSE70064A #5 LHO[ LHI LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 CYNSE70064A LHI LHO[ LHI LHO[ LHI ...
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... Figure 10-37. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 58 of 128 ...
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... Figure 10-38. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 59 of 128 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-39. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (This on device this global device.) winner.) ...
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... Figure 10-40. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss on (Miss on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 61 of 128 ...
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... Figure 10-41. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on this on this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 62 of 128 ...
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... Figure 10-42. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Hit but not on this winner.) device.) Search2 Search4 (Miss (Global on this winner ...
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... Figure 10-43. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on this on this device) device.) Search2 Search4 (Miss on (Miss on this device.) this device.) Page 64 of 128 ...
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... Figure 10-44. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on this on this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 65 of 128 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-45. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Global (Miss winner.) on this device.) Search2 Search4 (Miss (Hit ...
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... Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 Except Device 30 (the Last Device) CYNSE70064A cycle cycle cycle Search1 Search3 (Miss (Miss on this on this device.) device.) Search2 Search4 (Miss (Miss on on this this device.) device.) Page 67 of 128 ...
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... The GMR is the 136-bit word specified by the even and odd global mask pair selected by the GMR Index in the command’s cycle A. Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70064A cycle cycle cycle Search1 Search3 (Hit on (Hit on some some device device above.) above.) Search4 Search2 (Global miss ...
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... 1015806 CFG = 01010101 (136-bit configuration) Figure 10-48. ×136 Table with 31 Devices Max Table Size 16K × 136 bits 128K × 136 bits 496K × 136 bits Number of CLK Cycles CYNSE70064A 0 Odd B 0 (First matching entry) Latency in CLK Cycles Page 69 of 128 ...
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... Search on Tables Configured as û272 Using a Single CYNSE70064A Device Figure 10-49 shows the timing diagram for a Search command in the 272-bit-configured table (CFG = 10101010) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this Search subsystem is shown in Figure 10-50 ...
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... Document #: 38-02041 Rev. *F 271 271 CFG = 10101010 (272-bit configuration) Figure 10-51. ×272 Table with One Device Max Table Size 8K × 272 bits 64K × 272 bits 248K × 272 bits Number of CLK Cycles CYNSE70064A (First matching entry) Latency in CLK Cycles ...
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... Search on Tables x272-configured Using up to Eight CYNSE70064A Devices The hardware diagram of the Search subsystem of eight devices is shown in Figure 10-52. The following are the parameters programmed in the eight devices. • First seven devices (devices 0–6): CFG = 10101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 10-52. Hardware Diagram for a Table with Eight Devices Document #: 38-02041 Rev CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[1] BHI[2: CYNSE70064A #3 LHO[ CYNSE70064A # LHI LHI CYNSE70064A #5 LHO[ LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 CYNSE70064A LHI LHO[ LHI LHO[0] ...
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... Figure 10-53. Timing Diagram for 272-bit Search Device Number 0 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (This device is the global winner.) CYNSE70064A cycle cycle cycle Search2 Search3 (Miss (Miss on this on this device.) device.) Page 74 of 128 ...
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... Figure 10-54. Timing Diagram for 272-bit Search Device Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (Miss on this device.) CYNSE70064A cycle cycle cycle Search3 (Miss on this device.) Search2 (This device is global winner.) Page 75 of 128 ...
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... The 272-bit word K that is presented on the DQ bus in cycles and D of the command is compared to Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (Miss on this device.) CYNSE70064A cycle cycle cycle Search2 Search3 (Global (Miss miss.) on this device.) ...
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... The hardware diagram of the Search subsystem of 31 devices is shown in Figure 10-57. Each of the four blocks in the diagram represents a block of eight CYNSE70064A devices, except the last which has seven devices. The diagram for a block of eight devices is shown in Figure 10-58. The following are the parameters programmed into the 31 devices. ...
Page 78
... BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device for the Search operation. Table 10-31. Hit/Miss Assumption Search Number Block 0 Block 1 Block 2 Block 3 Document #: 38-02041 Rev Miss Miss Miss Miss Miss Hit Hit Hit CYNSE70064A 3 Miss Hit Hit Miss Page 78 of 128 ...
Page 79
... BHI[2] BHI[1] Block of 8 CYNSE70064As block 1 (devices 8–15) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70064As block 2 (devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70064As block 3 (devices 24–30) BHO[2] BHO[1] CYNSE70064A BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] ...
Page 80
... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] 3 Figure 10-58. Hardware Diagram for A Block Eight Devices Document #: 38-02041 Rev CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[ CYNSE70064A # CYNSE70064A #4 LHO[ LHI LHI CYNSE70064A #5 LHO[ LHI LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 CYNSE70064A LHI LHO[ LHI LHO[ LHI ...
Page 81
... Figure 10-59. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70064A cycle cycle cycle cycle cycle Search1 Search3 (Misson (Misson this device.) this device.) Search2 (Miss on this device.) Page 81 of 128 ...
Page 82
... Figure 10-60. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 (Miss on this device.) Page 82 of 128 ...
Page 83
... Figure 10-61. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70064A cycle cycle cycle Search1 Search3 (This device (Miss on global winner.) this device.) Search2 (Miss on this device.) Page 83 of 128 ...
Page 84
... Figure 10-62. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70064A cycle cycle cycle Search3 Search1 (Miss on (Miss on this device.) this device.) Search2 (Miss on this device.) Page 84 of 128 ...
Page 85
... Figure 10-63. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70064A cycle cycle cycle cycle cycle Search1 Search3 (Miss on this (Miss on device; hit in this device.) block 0 or 1.) Search2 (Miss on this device.) Page 85 of 128 ...
Page 86
... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-64. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70064A cycle cycle cycle Search3 Search1 (Hit but not (Miss on winner.) this device.) ...
Page 87
... Figure 10-65. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70064A cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 (Miss on this device.) Page 87 of 128 ...
Page 88
... Figure 10-66. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70064A cycle cycle cycle Search3 Search1 (Miss on (Miss on this device.) this device.) Search2 (Miss on this device.) Page 88 of 128 ...
Page 89
... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-67. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search1 Search3 CYNSE70064A cycle cycle cycle Search3 Search1 (Miss on (Global winner.) this device.) Search2 (Hit but not global winner.) ...
Page 90
... Figure 10-68. Timing Diagram for Devices Below the Winning Device in Block Number 3 Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search1 Search3 Except Device 30 (the Last Device) CYNSE70064A cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 (Miss on this device.) Page 90 of 128 ...
Page 91
... The GMR Index in cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles A and B. The GMR Index in cycle C selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles C and D. Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 (Hit on some device above.) CYNSE70064A cycle cycle cycle Search1 Search2 ...
Page 92
... Mixed-Sized Searches on Tables Configured with Different Widths Using an CYNSE70064A Device This subsection will cover mixed searches (×68, ×136, and ×272) with tables of different widths (×68, ×136, ×272). The sample operation shown is for a single device with CFG = 10010000 containing three tables of ×68, ×136, and ×272 widths. The operation can be generalized to a block of eight to 31 devices using four blocks ...
Page 93
... DQ[67:66 each of the and D cycles of the ×272-bit Search (Search3). By having table designation bits, the CYNSE70064A enables the creation of many tables in a bank of search engines of different widths. Figure 10-72 shows the sample table. Two bits in each 68-bit entry will need to designated as the table number bits. One example choice can be the 00 values for the table configured as × ...
Page 94
... The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The CYNSE70064A updates the signal after each Write or Learn command to a data array. The Learn command generates a Write cycle to the external SRAM, also using the NFA register as part of the SRAM address (see Section 12.0, “ ...
Page 95
... PHS_L CMDV CMD[1:0] CMD[8: SADR[21:0] CE_L 1 1 WE_L 0 OE_L 0 SSV 0 SSF Figure 10-73. Timing Diagram of Learn (TLSZ = 00) Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Learn2 Learn1 X Comp2 Comp1 TLSZ = 00, LRAM = 1, LDEV = 1. CYNSE70064A cycle cycle cycle Page 95 of 128 ...
Page 96
... DQ z SADR[21:0] z CE_L z WE_L z OE_L z SSV z SSF Figure 10-74. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01]) Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Learn2 Learn1 X Comp2 Comp1 TLSZ = 01, LRAM = 0, LDEV = 0. CYNSE70064A cycle cycle cycle Page 96 of 128 ...
Page 97
... At the end of cycle 2, a new instruction can begin. The latency of the SRAM Write is the same as the Search to the SRAM Read cycle measured from the second cycle of the Learn instruction. Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Learn1 X Learn2 Comp2 Comp1 Latency in CLK Cycles CYNSE70064A cycle cycle cycle Page 97 of 128 ...
Page 98
... The host ASIC must program the TLSZ to 01 for each eight devices in a block. This adds the required latency to allow time for the resolution about who drives the SRAM signals to take place. Only a single device drives the SRAM bus in any single cycle. Document #: 38-02041 Rev. *F CYNSE70064A Page 98 of 128 ...
Page 99
... CMDV CMD[8:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 11-1. Depth-Cascading to Form a Single Block Document #: 38-02041 Rev CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[1] BHI[2: CYNSE70064A #3 LHO[ CYNSE70064A # LHI LHI CYNSE70064A #5 LHO[ LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 CYNSE70064A LHI LHO[ LHI LHO[ ...
Page 100
... Depth-Cascading Devices (Four Blocks) Figure 11-2 shows how to cascade up to four blocks. Each block contains up to eight CYNSE70064A devices except the last, and the interconnection within each was shown in the previous subsection with the cascading eight devices in a block. Note. The interconnection between blocks for depth-cascading is important. The BHO signals of a device is connected to the BHI signal of the devices in all the downstream blocks ...
Page 101
... Section 7.0, “Registers” on page 13 of this specification, describes the NFA and SSR registers. ADR[14:0] contains the address supplied on the DQ bus during PIO access to the CYNSE70064A. Command bits 8, and 7 {CMD[8:7]} are passed from the command to the SRAM address bus. See Section 10.0, “Commands” on page 18, for more information. ID[4:0] is the ID of the device driving the SRAM bus (see Section 18.0, “ ...
Page 102
... During SRAM PIO Accesses, once the read or write command is given to the SRAM by the ASIC through the CYNSE70064A, the data transfer takes place directly between the ASIC and the SRAM using a seperate dedicated databus instead of through the CYNSE70064A ...
Page 103
... The following explains the SRAM Read operation completed through a table eight devices using the following parameters: TLSZ = 01. Figure 12-2 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved through CYNSE70064A device number 0. Figure 12-3 and Figure 12-4 show timing diagrams for device number 0 and device number 7, respectively. ...
Page 104
... CMD[8:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Document #: 38-02041 Rev CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[ CYNSE70064A #3 LHO[ CYNSE70064A # LHI LHI CYNSE70064A #5 LHO[ LHI LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 Figure 12-2. Table of a Block of Eight Devices CYNSE70064A LHI LHO[ LHI ...
Page 105
... ALE_L z z SADR z SSV z z SSF TLSZ = 01, HLAT = 000, LRAM = 0, LDEV = 0. Figure 12-3. SRAM Read Through Device Number Block of Eight Devices Document #: 38-02041 Rev. *F cycle cycle cycle cycle Read Address CYNSE70064A cycle cycle cycle Address driven by selected CYNSE70064A. Page 105 of 128 ...
Page 106
... TLSZ = 10. The diagram of such a table is shown in Figure 12-5. The following assumes that SRAM access is being accomplished through CYNSE70064A device number 0, that device number 0 is the selected device. Figure 12-6 and Figure 12-7 show the timing diagrams for device number 0 and device number 30, respectively. ...
Page 107
... BHI[2] BHI[1] Block of 8 CYNSE70064As Block 1 (devices 8–15) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70064As Block 2 (devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70064As Block 3 (devices 24–30) BHO[2] BHO[1] CYNSE70064A BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] ...
Page 108
... TLSZ = 10, HLAT = 010, LRAM = 0, LDEV =0 Figure 12-6. SRAM Read Through Device Number Bank of 31 Devices Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Read Address Address DQ driven by the selected CYNSE70064A (Device Number 0 Timing) CYNSE70064A cycle cycle cycle Page 108 of 128 ...
Page 109
... DQ[20:19] set select the SRAM address. Note that CMD[2] must be set to 0 for SRAM Write as burst Writes into the SRAM are not supported. • Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A. • Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A. ...
Page 110
... Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A. • Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A. At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM bus with the same latency as that of a Search instruction as measured from the second cycle of the Write command ...
Page 111
... CMD[8:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Document #: 38-02041 Rev CYNSE70064A #0 LHO[ CYNSE70064A #1 LHO[ CYNSE70064A #2 LHO[1] BHI[2: CYNSE70064A #3 LHO[ CYNSE70064A # LHI LHI CYNSE70064A #5 LHO[ LHI CYNSE70064A #6 LHO[ LHI LHI CYNSE70064A #7 Figure 12-9. Table of a Block of Eight Devices CYNSE70064A LHI LHO[ LHI LHO[0] ...
Page 112
... ALE_L z SADR[21:0] z ACK z SSV z SSF TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0 Figure 12-10. SRAM Write Through Device Number Block of Eight Devices Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Write Address x x Address CYNSE70064A cycle cycle cycle Page 112 of 128 ...
Page 113
... Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A. • Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A. At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM bus with the same latency as that of a Search instruction, as measured from the second cycle of the Write command ...
Page 114
... Block of 8 CYNSE70064As Block 1 (devices 8–15) BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 CYNSE70064As Block 2 (devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 CYNSE70064As Block 3 (devices 24–30) BHO[2] BHO[1] Figure 12-12. Table of 31 Devices (Four Blocks) CYNSE70064A GND BHI[0] SRAM BHO[0] BHI[0] ...
Page 115
... SSV z SSF TLSZ = 10, HLAT = XXX, LRAM = 0, LDEV = 0 Figure 12-13. SRAM Write Through Device Number 0 in Bank of 31 Devices (Device 0 Timing) Document #: 38-02041 Rev. *F cycle cycle cycle cycle cycle cycle cycle Write Address x x CYNSE70064A cycle cycle cycle Address z Page 115 of 128 ...
Page 116
... SSV 0 SSF TLSZ = 10, HLAT = XXX, LRAM = 1, LDEV = 1 Figure 12-14. SRAM Write Through Device Number 0 in Bank of 31 CYNSE70064A Devices 12.9 Timing Sequences for Back-to-Back Operations Table 12-2 shows the idle cycle requirements between operations. The operations in the second column represent operations already performed, and the operations in the first row are to be performed next ...
Page 117
... SEARCH READ WRITE No Wait / No Wait (TLSZ + No Wait [7] HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 2 2 and CLK2x cycles Figure 13-1. Power-up Sequence CYNSE70064A LEARN SRAM TLSZ /(TLSZ No Wait + HLAT and V DD DDQ have reached their steady state voltages. DDQ Page 117 of 128 ...
Page 118
... Application Figure 14-1 shows how a Search engine subsystem can be formed using a host ASIC and an CYNSE70064A bank. It also shows how this Search engine subsystem is integrated in a switch or router. The CYNSE70064A can access synchronous and asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in all search engines within a bank of search engines ...
Page 119
... MFID [11:1] 000_1101_1100 LSB [0] 16.0 Electrical Specifications This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing param- eters for the CYNSE70064A, as shown in Table 16-1 and Table 16-2. Table 16-1. DC Electrical Characteristics for CYNSE70064A Parameter Description I Input leakage current LI I ...
Page 120
... AC Timing Waveforms Table 17-1 shows the AC timing parameters for the CYNSE70064A device; Table 17-2 shows the same parameters but for 2.5V. Table 17-1. AC Timing Parameters with CLK2X Parameter Description f CLK2X frequency CLOCK t CLK2X period CLK [13] t CLK2X HIGH pulse CKHI ...
Page 121
... Figure 17-3. 2.5 I/O Output Load Equivalent for CYNSE70064A Figure 17-4 shows timing waveform diagrams. cycle cycle cycle 0 1 CLK2X CLK t ISCH Signal Group 0 t ISCH Signal t ISCH Group 1 t IHCH Signal Group 2 t ICSCH Signal Group 3 Signal Group 4 Signal Group 5 Signal Group 0: PHS_L, RST_L ...
Page 122
... Pinout Descriptions and Package Diagrams In the following figure and table the CYNSE70064A device pinout diagram and pinout descriptions are shown GND EOT ACK FULL NC FULO1 3 DQ64 DDQ DD DDQ 4 DQ62 NC V GND RSTL DQ60 V NC DQ66 DDQ DQ56 DQ58 DD 7 DQ50 ...
Page 123
... I/O D14 I/O D15 3.3V/2.5V D16 I/O D17 I/O D18 I/O D19 D20 1. Output-T E3 Output-T E4 Input E17 E18 CYNSE70064A Signal Name Signal Type DQ63 I/O DQ59 I/O DQ55 I/O VDDQ 3.3V/2.5V NC DQ39 I/O DQ35 I/O NC DQ23 I/O DQ19 I/O NC DQ11 I/O ...
Page 124
... R1 3.3V/2.5V R2 Output-T R3 1.8V R4 Input R17 1.8V R18 Input R19 1.8V R20 Output-T T1 Output-T T2 Output-T T3 Output T4 CYNSE70064A Signal Name Signal Type BHO1 Output BHO2 Output FULI0 Input CLK2X Input SAD21 Output-T VDDQ 3.3V/2.5V VDD 1.8V FULI1 Input FULI2 Input VDDQ 3.3V/2.5V FULI3 ...
Page 125
... Y11 3.3V/2.5V Y12 I/O Y13 I/O Y14 3.3V/2.5V Y15 I/O Y16 I/O Y17 3.3V/2.5V Y18 I/O Y19 3.3V/2.5V Y20 1.8V J9 J10 CYNSE70064A Signal Name Signal Type CMD8 Input GND Ground VDDQ 3.3V/2.5V NC VDDQ 3.3V/2.5V DQ46 I/O DQ42 I/O NC DQ34 I/O DQ28 ...
Page 126
... K10 GND K11 GND K12 GND L9 GND 19.0 Ordering Information Table 19-1 provides ordering information. Table 19-1. Ordering Information Part Number CYNSE70064A-50BGC CYNSE70064A-66BGC CYNSE70064A-83BGC Document #: 38-02041 Rev. *F Package Ball Signal Type Number Ground L10 Ground L11 Ground L12 Ground M9 Ground M10 ...
Page 127
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 272-lead PBGA ( 2.33 mm) BG272 Figure 20-1. Package CYNSE70064A 51-85130-*A Page 127 of 128 ...
Page 128
... Document History Page Document Title: CYNSE70064A Network Search Engine Document Number: 38-02041 REV. ECN NO. Issue Date ** 111438 02/21/02 *A 116610 07/10/02 *B 118153 09/19/02 *C 119282 11/19/02 *D 123686 02/20/03 *E 126020 05/08/03 *F 289735 See ECN Document #: 38-02041 Rev. *F Orig. of Change Description of Change AFX New data sheet ...