APA075-TQ100I MICROSEMI, APA075-TQ100I Datasheet - Page 38
APA075-TQ100I
Manufacturer Part Number
APA075-TQ100I
Description
Manufacturer
MICROSEMI
Datasheet
1.APA075-TQ100I.pdf
(178 pages)
Specifications of APA075-TQ100I
Family Name
ProASICPLUS®
Number Of Usable Gates
75000
# Registers
3072
# I/os (max)
66
Frequency (max)
180MHz
Process Technology
0.22um (CMOS)
Operating Supply Voltage (typ)
2.5V
Ram Bits
27648
Device System Gates
75000
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
2.7V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
APA075-TQ100I
Manufacturer:
ACTEL
Quantity:
1
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Calculating Typical Power Dissipation
ProASIC
of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following
formula:
Total Power Consumption—P
where:
Global Clock Contribution—P
P
for R < 15000 the model is: (P1 + (P2*R) – (P7*R2)) * Fs (lightly-loaded clock trees)
for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees)
where:
Storage-Tile Contribution—P
P
where:
2 -2 8
clock
storage
ProASIC
P
P
P
P
P10 =
P11 =
P5
ms =
Fs
P1
P2
P7
total
, the clock component of power dissipation, is given by the piece-wise model:
storage
dc
ac
Fs
R
, the storage-tile (Register) component of AC power dissipation, is given by
PLUS
=
=
= P
=
=
=
=
=
PLUS
=
=
= P5 * ms * Fs
dc
100 µW/MHz is the basic power consumption of the clock tree per MHz of the clock
1.3 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of the
clock
0.00003 µW/MHz is a correction factor for partially-loaded clock trees
device power is calculated with both a static and an active component. The active component is a function
7 mW for the APA075
8 mW for the APA150
11 mW for the APA300
12 mW for the APA450
12 mW for the APA600
13 mW for the APA750
19 mW for the APA1000
P
P
6850 µW/MHz is the basic power consumption of the clock tree per MHz of the clock
0.4 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of
the clock
the number of storage tiles clocked by this clock
the clock frequency
dc
clock
1.1 µW/MHz is the average power consumption of a storage tile per MHz of its output toggling rate.
The maximum output toggling rate is Fs/2.
the number of storage tiles (Register) switching during each Fs cycle
the clock frequency
Flash Family FPGAs
+ P
includes the static components of P
ac
+ P
storage
+ P
storage
logic
clock
total
+ P
outputs
+ P
inputs
VDDP
+ P
pll
+ P
v5.9
+ P
VDD
memory
+ P
AVDD
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