APA075-TQ100I MICROSEMI, APA075-TQ100I Datasheet - Page 39
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APA075-TQ100I
Manufacturer Part Number
APA075-TQ100I
Description
Manufacturer
MICROSEMI
Datasheet
1.APA075-TQ100I.pdf
(178 pages)
Specifications of APA075-TQ100I
Family Name
ProASICPLUS®
Number Of Usable Gates
75000
# Registers
3072
# I/os (max)
66
Frequency (max)
180MHz
Process Technology
0.22um (CMOS)
Operating Supply Voltage (typ)
2.5V
Ram Bits
27648
Device System Gates
75000
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
2.7V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
APA075-TQ100I
Manufacturer:
ACTEL
Quantity:
1
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Logic-Tile Contribution—P
P
where:
I/O Output Buffer Contribution—P
P
where:
I/O Input Buffer's Buffer Contribution—P
The input’s component of AC power dissipation is given by
where:
PLL Contribution—P
where:
RAM Contribution—P
Finally, P
where:
logic
outputs
P
P
P
P
P
P3
mc =
Fs
P4
C
p
Fp
P9
N
P6
N
F
E
, the logic-tile component of AC power dissipation, is given by
P8
q
Fq
logic
outputs
inputs
pll
memory
memory
memory
load
Pll
memory
, the I/O component of AC power dissipation, is given by
= P9 * N
memory
= P3 * mc * Fs
=
=
=
=
=
= P8 * q * Fq
= (P4 + (C
=
=
=
=
=
=
= P6 * N
1.4 μW/MHz is the average power consumption of a logic tile per MHz of its output toggling rate. The
maximum output toggling rate is Fs/2.
the number of logic tiles switching during each Fs cycle
the clock frequency
29 μW/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input
frequency.
the number of inputs
the average input frequency
, the memory component of AC power consumption, is given by
326 μW/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output
frequency. This is the total I/O current V
the output load
the number of outputs
the average output frequency
pll
7.5 mW. This value has been estimated at maximum PLL clock frequency.
number of PLLs used
=
=
=
=
memory
load
pll
175 µW/MHz is the average power consumption of a memory block per MHz of the clock
the number of RAM/FIFO blocks
(1 block = 256 words * 9 bits)
the clock frequency of the memory
the average number of active blocks divided by the total number of blocks (N) of the memory.
memory
* V
• Typical values for E
• In addition, an application-dependent component to E
* F
DDP
logic
9, 16, and 32 memory configuration
example, for a 1kx8 memory configuration using only 1 cycle out of 2, E
memory
2
)) * p * Fp
* E
outputs
memory
inputs
memory
DDP
would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8,
v5.9
.
memory
ProASIC
can be considered. For
PLUS
memory
Flash Family FPGAs
= 1/4*1/2 = 1/8
2-29
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