IS61C1024-15T ISSI, Integrated Silicon Solution Inc, IS61C1024-15T Datasheet - Page 8

• Manufacturer Part Number: IS61C1024-15T
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61C1024-15T

• Density: 1Mb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: TSOP-I
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 85mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

IS61C1024
IS61C1024L
AC WAVEFORMS
WRITE CYCLE NO. 1
8
WRITE CYCLE NO. 2
Notes:
1. The internal write time is defined by the overlap of
2. I/O will assume the High-Z state if
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the Write.
ADDRESS
ADDRESS
D
CE1
CE2
OUT
WE
D
D
CE1
CE2
OUT
IN
WE
D
OE
IN
LOW
HIGH
t
(
(
CE
SA
OE
DATA UNDEFINED
t
DATA UNDEFINED
SA
Controlled,
is HIGH During Write Cycle)
OE
= V
OE
IH
.
is HIGH or LOW)
t
VALID ADDRESS
HZWE
t
CE1
t
t
AW
HZWE
VALID ADDRESS
AW
t
t
PWE1
PWE2
LOW, CE2 HIGH and
t
t
t
t
t
PWE1
WC
SCE1
SCE2
WC
(1,2)
HIGH-Z
(1 )
Integrated Silicon Solution, Inc. — 1-800-379-4774
t
HIGH-Z
SD
DATA
t
SD
DATA
IN
IN
VALID
WE
VALID
LOW. All signals must be in valid states to
t
HD
t
t
HD
LZWE
t
LZWE
t
HA
t
HA
CE2_WR1.eps
CE2_WR2.eps
ISSI
SR028-1J
11/03/98
®