RC28F128J3C150 Intel, RC28F128J3C150 Datasheet - Page 69

• Manufacturer Part Number: RC28F128J3C150
• Manufacturer: Intel

Specifications of RC28F128J3C150

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 24/23Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 16M/8M
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

C.4
C.5
Datasheet
V
Block erase, program, and lock-bit configuration are not guaranteed if V
the specified operating ranges, or RP# ≠ V
program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of
t
will enter reset/power-down mode. The aborted operation may leave data partially corrupted after
programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase
and lock-bit configuration commands must be repeated after normal operation is restored. Device
power-off or RP# = V
The CUI latches commands issued by system software and is not altered by V
CE
power-down mode, or after V
during V
After block erase, program, or lock-bit configuration, even after V
the CUI must be placed in read array mode via the Read Array command if subsequent access to
the memory array is desired. V
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only
during device operation, but also for data retention during system idle time. Flash memory’s
nonvolatility increases usable battery life because data is retained when system power is removed.
PLPH
CC
2
transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/
+ t
, V
PHRH
CC
PEN
transitions.
until the reset operation is complete. Then, the operation will abort and the device
, RP# Transitions
IL
clears the Status Register.
CC
PEN
transitions below V
must be kept at or below V
IH
. If RP# transitions to V
LKO
. V
CC
CC
must be kept at or above V
PEN
during V
IL
transitions down to V
during block erase,
PEN
PEN
256-Mbit J3 (x8/x16)
or V
PEN
transitions.
CC
, CE
falls outside of
0
, CE
PEN
PENLK
1
, or
69
,