CY7C0831AV-133BBI Cypress Semiconductor Corp, CY7C0831AV-133BBI Datasheet - Page 7

• Manufacturer Part Number: CY7C0831AV-133BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0831AV-133BBI

• Density: 2Mb
• Access Time (max): 4.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 18b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Counter Reset Operation
All unmasked bits of the counter are reset to ‘0.’ All masked bits
remain unchanged. The mirror register is loaded with the value
of the burst counter. A Mask Reset followed by a Counter Reset
resets the counter and mirror registers to 00000, as does master
reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
When the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a ‘1’ for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are ‘1,’ the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being ‘1s,’ a counter interrupt flag
(CNTINT) is asserted. The next Increment returns the counter
register to its initial value, which was stored in the mirror register.
The counter address can instead be forced to loop to 00000 by
externally connecting CNTINT to CNTRST.
results in one or more of the unmasked bits of the counter being
‘0’ deasserts the counter interrupt flag. The example in
on page 10 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit ‘0’ as the LSB
and bit ‘16’ as the MSB. The maximum value the mask register
can be loaded with is 3FFFFh. Setting the mask register to this
value allows the counter to access the entire memory space. The
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)
Document #: 38-06059 Rev. *S
Notes
18. Counter operation and mask register operation is independent of chip enables.
19. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
CLK
X
MRST
H
H
H
H
H
H
H
H
H
L
CNT/MSK
H
H
H
H
H
X
L
L
L
L
CNTRST
X
H
H
H
H
H
H
H
L
L
[19]
An increment that
ADS
X
X
H
H
X
H
L
L
L
L
CNTEN
Figure 4
H
H
H
X
X
L
L
X
L
X
Master Reset
Counter Reset
Counter Load
Counter Readback
Counter Increment
Counter Hold
Mask Reset
Mask Load
Mask Readback
Reserved
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
after the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value until it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT is issued when the counter reaches
its maximum value
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all ‘1s.’ It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid t
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) are three-stated.
block diagram of the operation.
Operation
CY7C0832BV, CY7C0833AV
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
Reset address counter to all 0s and mask
register to all 1s.
Reset counter unmasked portion to all 0s.
Load counter with external address value
presented on address lines.
Read out counter internal value on address
lines.
Internally increment address counter value.
Constantly hold the address value for multiple
clock cycles.
Reset mask register to all 1s.
Load mask register with value presented on
the address lines.
Read out mask register value on address
lines.
Operation undefined
[17, 18]
Description
Figure 3
on page 9 shows a
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CA2
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