IS62LV256-70TI ISSI, Integrated Silicon Solution Inc, IS62LV256-70TI Datasheet - Page 8

• Manufacturer Part Number: IS62LV256-70TI
• Description: SRAM 256K 32Kx8 70ns 3.3v
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: Asynchronousr

Specifications of IS62LV256-70TI

• Density: 256Kb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: TSOP-I
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 30mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 32K
• Memory Size: 256 Kbit
• Access Time: 70 ns
• Package / Case: TSOP I-28
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 30 mA
• Organization: 32 K x 8
• Interface: TTL
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: Not Compliant

IS65LV256AL
IS62LV256AL
WRITE CYCLE NO. 2 (CE Controlled)
8
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
D
OUT
WE
D
CE
IN
DATA UNDEFINED
t
SA
≥
V
Ih
.
(1,2)
Integrated Silicon Solution, Inc. — www.issi.com —
t
HZWE
t
AW
t
t
SCE
PWE
t
WC
HIGH-Z
t
SD
DATA-IN VALID
t
HA
t
t
HD
LZWE
1-800-379-4774
10/23/06
Rev. B