FW21154AE Intel, FW21154AE Datasheet - Page 7
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FW21154AE
Manufacturer Part Number
FW21154AE
Description
Manufacturer
Intel
Datasheet
1.FW21154AE.pdf
(36 pages)
Specifications of FW21154AE
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Package Type
BGA
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant
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21154 PCI-to-PCI Bridge Specification Update
12/14/99
9/18/00
8/11/99
7/29/99
7/19/99
2/7/00
9/1/99
Date
Version
007
006
005
004
003
002
001
Modified description of trst_l, tms and tdi signal, added a new section on JTAG
testing. Modified the description of the trst_l specification clarification. Modified
order of serial stream in Figure 20, Clock Mask and Load Timing. Added note for
pull-up resistor for output clocks. Added specification change to PBGA package
dimensions for coplanarity maximum value. Added documentation changes 21
and 22: descriptions of two signals when secondary bus speed set for 66 MHz.
Modified order of serial stream in table 34, gpio Serial Data format. Modified the
description for Dword bit 0. Modified Figure 19, Example of gpio Clock Mask
Implementation on the System Board. Modified Figure 20, Clock Mask and Load
Shift Timing. Clarified definition of trst_l signal.
Modified description of the clamp circuit errata. Added 64-bit data bus width
errata.
Added documentation change item 6 for 66 MHz operation. Updated Hold time
errata. Added clamp circuit errata.
Tsetup test conditions found to be invalid. Device meets 3 ns Tsetup limit on all
pins.
Added updated boundary scan order pin list.
This is the new Specification Update document. It contains all identified errata
published prior to this date.
Description
Revision History
Intel Confidential7