21154BC Intel, 21154BC Datasheet - Page 6

• Manufacturer Part Number: 21154BC
• Manufacturer: Intel

Specifications of 21154BC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Revision History
6Intel Confidential
12/15/00
11/13/00
10/02/00
4/30/01
5/8/01
Date
Version
012
010
009
008
011
Added information for AE and BE versions of the 21154 product
Updated Errata #5 AC Marking state in
Updated status state for Errata #4, #5, #6, and #8 in
and in descriptions in
Updated descriptions for Errata #1 and #3 in
Added last two rows to
Updated description for
Signals. Tval timing improved on the 21154BE.” on page 15
Updated description for
Control) on the 21154.” on page 16
Added changes #2, #3, and #4 in
Added
The Steppings columns in the
“Specification Clarifications”
accurately reflect the revisions of the component.
Errata #3 (Setup Issues With PCI Control Signals When Running at 66 MHz on
the 21154BC) of this Specification Update was found to be invalid and is now
listed as Fixed.
The term “REV_ID6” was removed from the problem section of Errata 3,
Issues With PCI Control Signals When Running at 66 MHz on the 21154BC.
page
Errata 7,
added.
Errata 8,
Sets.
Documentation Changes 12,
15, and 18,
documentation change 15,
66 MHz Operation
Documentation changes 17, 18, and 19, referenced the wrong document number.
The correct document number has been updated in the
Changes. All references to the 21554 have been changed to 21154. Figures in
documentation changes
stepping C included as an errata in the
Corrected speed settings for 21154AB/AC/BC Markings.
Added errata 6.
•
•
•
•
•
“Updated Version of PCI Local Bus Specification” on page 35
“Section 4.1, Updated s_clk and p_clk description” on page 35
“Section 4.2, Updated Clock Outputs” on page 35
“Section 4.4.1, Added Note at End of Section.” on page 35
“Section 4.5, Table 5 Product Part Numbers have been updated.” on
page
16.
was added.
toTable , “Documentation Changes” on page 13
Note:
GPIO 66 MHz Timing May Cause Secondary Clocks to be Disabled
Bus Conflict Occurs During Configuration on AGP Port of Some Chip
36.
Section 4.4.1, Serial Clock Mask Shift, Figure 3
These documentation changes have been implemented in
Version 003 of the 21154 PCI-to-PCI Bridge Hardware
Implementation Application Note.
was added.
“Errata” on page 15
Table 1, “21154 Markings” on page 14
“Tval Timing Issues When Running at 66 MHz for All PCI
“Hold Time Issues for All PCI Signals (Both Bused and
13
Section 10.2.1, Mask and Load Shift Timing Events for
21154 PCI-to-PCI Bridge Specification Update
and
on
Section 10.2, Secondary Clock Control, Figure
“Errata”
page 11
20
“Specification Changes” on page 22
Description
have been updated. Errata
table,
Summary Table of
Table , “Errata” on page 11
were changed to Markings to more
“Specification Changes”
Table , “Errata” on page 11
Table , “Errata” on page 11
that include:
Summary Table of
Changes.
were modified, and
3
now has
table, and
Setup
19,
on
was