DSP56002FC66 Freescale Semiconductor, DSP56002FC66 Datasheet - Page 50
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DSP56002FC66
Manufacturer Part Number
DSP56002FC66
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.DSP56002FC66.pdf
(110 pages)
Specifications of DSP56002FC66
Device Core Size
24b
Architecture
Harvard
Format
Fixed Point
Clock Freq (max)
66MHz
Mips
33
Device Input Clock Speed
66MHz
Ram Size
3KB
Program Memory Size
1.5KB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSP56002FC66
Manufacturer:
MOTOROLA
Quantity:
5 530
Company:
Part Number:
DSP56002FC66
Manufacturer:
MOTOROLA
Quantity:
6 250
Company:
Part Number:
DSP56002FC66
Manufacturer:
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Quantity:
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Part Number:
DSP56002FC66
Manufacturer:
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Quantity:
20 000
Company:
Part Number:
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Manufacturer:
AD
Quantity:
92
No.
115 Delay from BR
116 Delay from BR
Specifications
External Bus Asynchronous Timing
EXTERNAL BUS ASYNCHRONOUS TIMING
C
WS = Number of Wait States (0 to 15), as determined by BCR register
Capacitance Derating: The DSP56002 External Bus Timing Specifications are designed and
tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive
capability of the External Bus pins (A0–A15, D0–D23, PS, DS, RD, WR, X/Y, EXTP) derates
linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C
pins (HI, SCI, SSI, and Timer) derate linearly at 1 ns per 5 pF of additional capacitance from 50
pF to 250 pF of loading. Active low lines should be “pulled up” in a manner consistent with the
AC and DC specifications.
2-24
L
Assertion to BG
Assertion
Deassertion to BG
Deassertion
= 50 pF + 2 TTL loads
•
•
•
•
•
Characteristics
With no
external access
from the DSP
During external
read or write
access
During external
read-modify-
write access
During Stop
mode—
external bus
will not be
released and
BG will not go
low
During Wait
mode
Table 2-12 External Bus Asynchronous Timing
T
T
2T
C
C
Min
2T
T
T
+ T
+ T
C
H
H
Freescale Semiconductor, Inc.
C
+
H
H
For More Information On This Product,
40 MHz
(2T
(T
4T
T
4T
6T
C
4T
C
C
C
DSP56002/D, Rev. 3
+ T
C
C
+ T
C
Max
WS) + 14
+ T
+ T
14
WS) +14
+ 12.5
Go to: www.freescale.com
H
H
H
H
+ 15
+ 14
+
+
T
T
2T
C
C
Min
2T
T
T
+ T
+ T
C
H
H
C
+
H
H
66 MHz
(2T
(T
4T
T
4T
6T
C
4T
C
C
C
+ T
C
C
C
+ T
Max
WS) + 14
+ T
+ T
14
WS) +14
+ 12.5
H
H
H
H
+ 15
+ 14
+
+
T
T
2T
C
C
Min
2T
T
T
+ T
+ T
C
H
H
C
+
H
H
80 MHz
(2T
(T
4T
T
4T
6T
C
4T
C
C
C
MOTOROLA
+ T
C
C
+ T
C
Max
WS) + 14
+ T
+ T
14
WS) +14
+ 12.5
H
H
H
H
+ 15
+ 14
+
+
Unit
ns
ns
ns
ns
ns
ns