GE28F320C3BD70 Intel, GE28F320C3BD70 Datasheet - Page 46

• Manufacturer Part Number: GE28F320C3BD70
• Manufacturer: Intel

Specifications of GE28F320C3BD70

• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

Table 24: Command Codes and Descriptions
Datasheet
46
Note:
(HEX)
Code
D0
40
20
B0
70
50
90
60
01
2F
98
C0
10
00
FF
See
Read Array
Program Set-Up
Erase Set-Up
Erase Confirm
Program/Erase
Resume
Unlock Block
Program Suspend
Erase Suspend
Read Status
Register
Clear Status
Register
Read Identifier
Block Lock,
Block Unlock,
Block Lock-Down
Set-Up
Lock-Block
Lock-Down
CFI Query
Protection
Program
Set-Up
Alt. Prog Set-Up
Invalid/
Reserved
Device Mode
Appendix A, “Write State Machine States”
This command places the device in read-array mode, which outputs array data on the data pins.
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second
cycle latches addresses and data information and initiates the WSM to execute the Program
algorithm. The flash outputs Status Register data when CE# or OE# is toggled. A Read Array
command is required after programming to read array data. See
Mode” on page 43
This is a two-cycle command. It prepares the CUI for the Erase Confirm command. If the next
command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 to “1,”
(b) place the device into the read-Status Register mode, and (c) wait for another command. See
Section 10.3, “Erase Mode” on page 44
If the previous command was an Erase Set-Up command, then the CUI will close the address and
data latches and begin erasing the block indicated on the address pins. During program/erase, the
device will respond only to the Read Status Register, Program Suspend and Erase Suspend
commands, and will output Status Register data when CE# or OE# is toggled.
If a Program or Erase operation was previously suspended, this command will resume that
operation.
If the previous command was Block Unlock Set-Up, the CUI will latch the address and unlock the
block indicated on the address pins. If the block had been previously set to Lock-Down, this
operation will have no effect. (See
Issuing this command will begin to suspend the currently executing Program/Erase operation. The
Status Register will indicate when the operation has been successfully suspended by setting either
the program-suspend SR[2] or erase-suspend SR[6] and the WSM status bit SR[7] to a “1”
(ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input-
control pins except RP#, which will immediately shut down the WSM and the remainder of the chip
if RP# is driven to V
This command places the device into read-Status Register mode. Reading the device will output
the contents of the Status Register, regardless of the address presented to the device. The device
automatically enters this mode after a Program or Erase operation has been initiated. See
Section 10.1.4, “Read Status Register” on page 42
The WSM can set the block-lock status SR[1], V
status SR[5] bits in the Status Register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
This command puts the device into the read-identifier mode so that reading the device will output
the manufacturer/device codes or block-lock status. See
on page 41
This command prepares the CUI for block-locking changes. If the next command is not Block
Unlock, Block Lock, or Block Lock-Down, then the CUI will set both the program and erase-Status
Register bits to indicate a command-sequence error. See
on page 48
If the previous command was Lock Set-Up, the CUI will latch the address and lock the block
indicated on the address pins. (See
If the previous command was a Lock-Down Set-Up command, the CUI will latch the address and
lock-down the block indicated on the address pins. (See
This command puts the device into the CFI-Query mode so that reading the device will output
Common Flash Interface information. See
Flash Interface”
This is a two-cycle command. The first cycle prepares the CUI for a program operation to the
protection register. The second cycle latches addresses and data information and initiates the WSM
to execute the Protection Program algorithm to the protection register. The flash outputs Status
Register data when CE# or OE# is toggled. A Read Array command is required after programming
to read array data. See
Operates the same as Program Set-up command. (See 0x40/Program Set-Up)
Unassigned commands should not be used. Numonyx reserves the right to redefine these codes
for future functions.
.
.
IL
.
. See Sections 3.2.5.1 and 3.2.6.1.
.
Section 11.5
Section 11.1
Section 11.1
Command Description
for mode transition information.
.
Section 10.1.3
PP
Status SR[3], program status SR[4], and erase-
.
)
)
Section 10.1.2, “Read Identifier”
Section 11.1
Section 11.0, “Security Modes”
and
.
Section 10.2, “Program
Appendix C, “Common
)
C3 Discrete
March 2008
290645-24