DA82562EM Intel, DA82562EM Datasheet - Page 44
DA82562EM
Manufacturer Part Number
DA82562EM
Description
Manufacturer
Intel
Datasheet
1.DA82562EM.pdf
(173 pages)
Specifications of DA82562EM
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Host Software Interface
6.3.2.2
36
Table 13. SCB Status Word Bits Descriptions
Figure 10. SCB Command Word
Note: The SCB Status word is not updated immediately in response to SCB commands. For example, the
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
CU status will remain in the idle state for a period of time after the CU start command is issued.
Software should not rely exclusively on the state of the SCB Status word to determine when it is
appropriate to issue commands requiring the device to be in a specific state. Software may be
required to keep an internal state engine on the commands recently issued to the device to insure
that data read from the register is valid.
SCB Command Word
The SCB Command word is also addressable as two bytes. The upper byte is called the Interrupt
Control byte. The least significant byte is called the Command byte.
The Interrupt Control byte allows software to either force the generation of an interrupt or mask
device interrupts from occurring. The 82558 and later devices also allow individual interrupt
sources from within the device to be masked (this feature is not available in the 82557).
Bit
Bits 7:6
Bits 5:2
Bits 1:0
31
Specific Interrupt Mask Bits
Symbol
CUS
RUS
Reserved
Description
This field contains the CU status (2 bits). Valid values are for this field are:
This field contains the RU status (4 bits). Valid values are:
These bits are reserved and should not be used.
00
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
HQP Active
Idle
Suspended
LPQ Active
26
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Idle
Suspended
No resources
Ready
Reserved
Reserved
Reserved
Reserved
SI
25
M
24
23
CU Command
20
0
19
18
RU Command
16
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