TE28F128J3C150 Intel, TE28F128J3C150 Datasheet - Page 51

• Manufacturer Part Number: TE28F128J3C150
• Manufacturer: Intel

Specifications of TE28F128J3C150

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 24/23Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 16M/8M
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Table 22. STS Configuration Coding Definitions
10 = pulse on Program Complete
11 = pulse on Erase or Program
NOTES:
1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.
2. An invalid configuration code will result in both SR.4 and SR.5 being set.
D[1:0] = STS Configuration Codes
D7
Complete
D6
D5
Reserved
Used to generate a system interrupt pulse when any flash device in
an array has completed a program operation. Provides highest
performance for servicing continuous buffer write operations.
Used to generate system interrupts to trigger servicing of flash arrays
when either erase or program operations are completed, when a
common interrupt service routine is desired.
D4
D3
Notes
D2
256-Mbit J3 (x8/x16)
Complete
Pulse on
Program
D1
(1)
Complete
Pulse on
Erase
D0
(1)
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