GD82559C Intel, GD82559C Datasheet - Page 22

• Manufacturer Part Number: GD82559C
• Manufacturer: Intel

Specifications of GD82559C

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Mounting: Surface Mount
• Pin Count: 241
• Lead Free Status / Rohs Status: Not Compliant

Intel-Based Electronic Classroom Student Computing Station
5.7.2.2
5.7.2.3
5.7.2.4
5.8
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Remote Service Boot
The WfM Baseline specifies the protocols by which a client requests and downloads an executable
image from a server and the minimum requirements on the client execution environment when the
downloaded image is executed. The Baseline specification includes a set of APIs for the particular
network controller used. The code supporting the Preboot eXecution Environment (PXE) and the
network controller is provided on the EtherExpress™ PRO/100 WfM adapters Option ROM. Two
implementation options are available:
In addition, the BIOS must provide the _SYSID_ and _UUID_ data structures. The details of the
BIOS requirements can be obtained from the Intel web site:
Remote Wake-Up
If a student computing station supports a reduced power state, it is possible to bring the system to a
fully powered state in which all power management interfaces are available. Typically, the LAN
adapter recognizes a special packet as a signal to wake up the system. The system BIOS must
enable the wake event and provide wake up status. The details of the BIOS requirements can be
obtained from the Intel web site:
Power Management
WfM Baseline compliant systems have four distinct power states: Working, Sleeping, Soft Off, and
Mechanical Off. A user accessible switch that will send a soft off request to the system usually
provides Soft Off. A second optional “override” switch located in a less obvious place (or removal
of the power cord) stops current flow forcing the platform into the mechanical off state without OS
consent. Note that a second “override” switch is required for legal reasons in some jurisdictions
(for example, some European countries). The BIOS may support the power management
requirement either through the APM revision 1.2 or ACPI revision 1.0 specifications. See Intel's
web site for additional information:
Low Pin Count (LPC) Interface
In the Intel 810 chipset platform, the Super I/O* (SIO) component has migrated to the Low Pin
Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs.
The LPC Super I/O component requires the same feature set as traditional Super I/O components.
It should include a keyboard and mouse controller, a floppy disk controller, and serial and parallel
ports. In addition to the Super I/O features, an integrated game port is recommended because the
AC’97 interface does not provide support for a game port. In systems that have ISA audio, the
game port typically existed on the audio card. The fifteen pin game port connector provides for two
joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a
comprehensive list of devices offered and features supported.
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NIC with Option ROM and Wake on LAN Header
LAN on Motherboard implementation.
For this option, the Preboot execution environment and the network controller code must be
incorporated into the system BIOS.
http://developer.intel.com/ial/WfM/design/pxedt/index.htm
http://developer.intel.com/ial/WfM/design/rwudt/index.htm
http://developer.intel.com/ial/WfM/design/pmdt/index.htm.
Application Note