RC28F640J3C115 Intel, RC28F640J3C115 Datasheet - Page 50

• Manufacturer Part Number: RC28F640J3C115
• Manufacturer: Intel

Specifications of RC28F640J3C115

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 115ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4M
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

256-Mbit J3 (x8/x16)
14.0
14.1
14.2
50
Table 22. STS Configuration Coding Definitions
Special Modes
This section describes how to read the status, ID, and CFI registers. This section also details how to
configure the STS signal.
Set Read Configuration Register Command
This command is no longer supported on J3A or J3C. The J3A device will ignore this command,
while the J3C device will result in an invalid command sequence (SR.4 and SR.5 =1).
Status (STS)
The Status (STS) signal can be configured to different states using the Configuration command.
Once the STS signal has been configured, it remains in that configuration until another
configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/
BY# operation where RY/BY# low indicates that the WSM is busy. RY/BY# high indicates that the
state machine is ready for a new operation or suspended.
Definitions” on page 50
To reconfigure the Status (STS) signal to other modes, the Configuration command is given
followed by the desired configuration code. The three alternate configurations are all pulse mode
for use as a system interrupt as described below. For these configurations, bit 0 controls Erase
Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00
configuration code with the Configuration command resets the STS signal to the default RY/BY#
level mode. The possible configurations and their usage are described in
Configuration Coding Definitions” on page
when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration
code will result in both SR.4 and SR.5 being set. When configured in one of the pulse modes, the
STS signal pulses low with a typical pulse width of 250 ns.
00 = default, level mode;
01 = pulse on Erase Complete
D[1:0] = STS Configuration Codes
D7
device ready indication
D6
displays the possible STS configurations.
D5
Reserved
Used to control HOLD to a memory controller to prevent accessing a
flash memory subsystem while any flash device's WSM is busy.
Used to generate a system interrupt pulse when any flash device in
an array has completed a block erase. Helpful for reformatting blocks
after file system free space reclamation or “cleanup.”
D4
50. The Configuration command may only be given
D3
Table 22, “STS Configuration Coding
Notes
D2
Table 22, “STS
Complete
Pulse on
Program
D1
(1)
Datasheet
Complete
Pulse on
Erase
D0
(1)