DT28F320S3110 Intel, DT28F320S3110 Datasheet - Page 11

• Manufacturer Part Number: DT28F320S3110
• Manufacturer: Intel

Specifications of DT28F320S3110

• Density: 32Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 2.7/3.3/5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

Commands are written using standard micro-
processor write timings. The CUI contents serve
as input to the WSM that controls the block
erase, programming, and lock-bit configuration.
The internal algorithms are regulated by the
WSM,
verification, and margining of data. Addresses
and data are internally latched during write
cycles. Writing the appropriate command outputs
array data, identifier codes, or Status Register
data.
Interface
progress of block erase, programming, and lock-
bit configuration can be stored in any block. This
code is copied to and executed from system
RAM
successful completion, reads are again possible
via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read or write data from any other
block. Program suspend allows system software
to suspend a program to read data from any
other flash memory array location.
ADVANCE INFORMATION
during
including
software
flash
pulse
that
memory
initiates
repetition,
updates.
and
internal
Figure 5. Memory Map
polls
After
2.1
Depending on the application, the system
designer may choose to make the V
supply switchable or hardwired to V
device supports either design practice, and
encourages
memory interface.
When V
altered. When high voltage is applied to V
two-step block erase, program, or lock-bit
configuration
protection from unwanted operations. All write
functions are disabled when V
the write lockout voltage V
V
provides additional protection from inadvertent
code or data alteration.
IL
.
The
PP
Data Protection
device’s
V
optimization
PPLK
command
, memory contents cannot be
block
28F160S3, 28F320S3
LKO
sequences
of
CC
locking
or when RP# is at
the
voltage is below
PPH1/2
processor-
PP
capability
provide
PP
power
. The
, the
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