CY7C4285-10ASI Cypress Semiconductor Corp, CY7C4285-10ASI Datasheet

CY7C4285-10ASI

Manufacturer Part Number
CY7C4285-10ASI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4285-10ASI

Configuration
Dual
Density
1.125Mb
Access Time (max)
8ns
Word Size
18b
Organization
64Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
55mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant
285
Cypress Semiconductor Corporation
Document #: 38-06008 Rev. *A
Features
• High-speed, low-power, first-in first-out (FIFO)
• 32K x 18 (CY7C4275)
• 64K x 18 (CY7C4285)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
• Low power
• Fully asynchronous and simultaneous read and write
• Empty, Full, Half Full, and programmable Almost Empty
• TTL compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 68-pin PLCC and 64-pin 10x10 TQFP
• Pin-compatible density upgrade to CY7C42X5
• Pin-compatible density upgrade to
Logic Block Diagram
memories
times)
operation
and Almost Full status flags
families
IDT72205/15/25/35/45
— I
— I
CC
SB
=50 mA
= 2 mA
WXO/HF
FL/RT
RXO
WXI
RXI
RS
WCLK
EXPANSION
CONTROL
POINTER
WRITE
WRITE
RESET
LOGIC
LOGIC
WEN
3901 North First Street
OUTPUT REGISTER
THREE–STATE
REGISTER
ARRAY
32Kx18
64Kx18
D
INPUT
Q
RAM
0 –17
0 – 17
Functional Description
The CY7C4275/85 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4275/85 have an output
enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to 100
MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
es should be tied to V
32K/64Kx18 Deep Sync FIFOs
OE
RCLK
San Jose
PROGRAM
REGISTER
CONTROL
POINTER
FLAG
LOGIC
READ
READ
FLAG
REN
CC
.
SS
4275–1
and the FL pin of all the remaining devic-
FF
EF
PAE
PAF
SMODE
CA 95134
Revised December 26, 2002
CY7C4275
CY7C4285
408-943-2600
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Related parts for CY7C4285-10ASI

CY7C4285-10ASI Summary of contents

Page 1

... Features • High-speed, low-power, first-in first-out (FIFO) memories • 32K x 18 (CY7C4275) • 64K x 18 (CY7C4285) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — — • Fully asynchronous and simultaneous read and write operation • ...

Page 2

... The Almost Empty/Almost Full flags become synchronous if the V configurations are fabricated using an advanced 0.5 CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. 7C4275/85-10 7C4275/85-15 100 66 0 CY7C4285 64K x 18 64-pin 10x10 TQFP, 68-pin PLCC CY7C4275 CY7C4285 TQFP GND ...

Page 3

... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual-Mode Pin Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4275 CY7C4285 /SMODE is tied CC /SMODE is tied ...

Page 4

... 8 2 –0.5 0 Max. –10 + > –10 + < V < Com’l 50 Ind 55 Com’l 2 Ind 2 Test Conditions MHz 5.0V CC CY7C4275 CY7C4285 Ambient Temperature + 10% – + 10% 7C42X5-5 7C42X5-25 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 V 2 –0.5 0.8 –0.5 0.8 V –10 +10 –10 +10 A –10 +10 – ...

Page 5

... Equivalent to: THÉ VENIN EQUIVALENT 410 OUTPUT 7C42X5-10 Min. Max. 100 2 10 4.5 4.5 3 0 [12 [12] 3 [13] /SMODE tied /SMODE tied [13] /SMODE tied OHZ . PAF(E) CY7C4275 CY7C4285 90% 90% 10% 10 4275–5 1.91V 7C42X5-15 7C42X5-25 Min. Max. Min. Max. Unit 66.7 40 MHz ...

Page 6

... SKEW2 Empty Flag t Skew Time between Read Clock and Write Clock for SKEW3 Programmable Almost Empty and Programmable Al- most Full Flags (Synchronous Mode only) Document #: 38-06008 Rev. *A 7C42X5-10 Min. Max. 8 /SMODE tied 4 CY7C4275 CY7C4285 7C42X5-15 7C42X5-25 Min. Max. Min. Max. Unit 6 ...

Page 7

... VALID DATA t OE [15] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4275 CY7C4285 NO OPERATION t WFF 4275–6 t REF t OHZ 4275–7 Page [+] Feedback ...

Page 8

... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06008 Rev RSR t RSF t RSF t RSF [18] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4275 CY7C4285 [17] OE=1 OE=0 4275– [19 4275–9 (maximum) = either 2 FRL CLK SKEW2 CLK SKEW2 Page [+] Feedback ...

Page 9

... REN LOW DATA IN OUTPUT REGISTER Q – Document #: 38-06008 Rev ENS REF REF SKEW2 [14 SKEW1 DATA WRITE t WFF t ENS DATA READ CY7C4275 CY7C4285 t ENH [18] t FRL t REF D0 4275–10 NO WRITE DATA WRITE t WFF t ENH t A NEXT DATA READ 4275–11 Page [+] Feedback ...

Page 10

... PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06008 Rev CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE ENS t CLKL t t ENS ENH t PAE WORDS IN FIFO t PAE t ENS CY7C4275 CY7C4285 HALF FULLOR LESS 4275–12 n WORDS IN FIFO 4275–13 Page [+] Feedback ...

Page 11

... If a read is preformed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 32768 25. PAF is offset = m. 26. 32768 m words in CY7C4275 and 65536 – m words in CY7C4285. 27. 32768 ( words in CY7C4275 and 65536 – CY7C4285. Document #: 38-06008 Rev CLKL t ...

Page 12

... Note 28 t ENH Note 29 t PAF FULL– M WORDS IN FIFO t SKEW3 t ENS t CLKL t ENH t DH PAF OFFSET (m 1) words of the FIFO when PAF goes LOW. CY7C4275 CY7C4285 [26] t [30] PAF synch t t ENS ENH 4275–16 PAE OFFSET – 4275–17 Page [+] Feedback ...

Page 13

... WXI t WCLK Notes: 31. Write to last physical location. 32. Read from last physical location. Document #: 38-06008 Rev CLKL t ENH t A UNKNOWN PAE OFFSET Note Note Note XIS CY7C4275 CY7C4285 PAF OFFSET PAE OFFSET 4275–18 4275–19 4275–20 4275–21 Page [+] Feedback ...

Page 14

... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06008 Rev XIS t PRT t RTR . RTR to update these flags. RTR CY7C4275 CY7C4285 4275–22 4275–23 Page [+] Feedback ...

Page 15

... When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. CY7C4275 CY7C4285 [36] Selection Writing to offset registers: Empty Offset ...

Page 16

... Notes: 37 Empty Offset (Default Values: CY7C4275/CY7C4285 n = 127). 38 Full Offset (Default Values: CY7C4275/CY7C4285 n = 127). Document #: 38-06008 Rev. *A nal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t after the retransmit pulse ...

Page 17

... RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C4275/85s. RESET (RS) 18 7C4275 7C4285 FIRST LOAD (FL) WRITE EXPANSION IN (WXI) CY7C4275 CY7C4285 READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAF) EMPTY FLAG (EF) DATA OUT ( 4275–24 Page [+] Feedback ...

Page 18

... WXO RXO 7C4275 7C4285 PAE PAF WXI RXI WXO RXO 7C4275 7C4285 PAF PAE WXI RXI READ CLOCK (RCLK) WXO RXO READ ENABLE (REN) 7C4275 7C4285 OUTPUTENABLE (OE PAE PAF WXI RXI CY7C4275 CY7C4285 DATA OUT (Q) EF PAE 4275–25 Page [+] Feedback ...

Page 19

... Package Name Type A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack CY7C4275 CY7C4285 Operating Range Commercial Industrial Commercial Commercial Operating Range Commercial Industrial Commercial Commercial ...

Page 20

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4275 CY7C4285 Page [+] Feedback ...

Page 21

... Document Title: CY7C4275, CY7C4285 32K/64K X 18 Deep Sync FIFOs Document Number: 38-06008 Issue REV. ECN NO. Date Change ** 106469 07/12/01 *A 122260 12/26/02 Document #: 38-06008 Rev. *A Orig. of Description of Change SZV Change from Spec Number: 38-00588 to 38-06008 RBI Power up requirements added to Maximum Ratings Information ...

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