A42MX24-PQ208 MICROSEMI, A42MX24-PQ208 Datasheet - Page 65

• Manufacturer Part Number: A42MX24-PQ208
• Manufacturer: MICROSEMI

Specifications of A42MX24-PQ208

• Family Name: 42MX
• Number Of Usable Gates: 36000
• Number Of Logic Blocks/elements: 912
• # Registers: 1410
• # I/os (max): 176
• Process Technology: 0.45um (CMOS)
• Operating Supply Voltage (typ): 3.3/5V
• Logic Cells: 912
• Device System Gates: 36000
• Propagation Delay Time: 2.5/1.8ns
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Table 35 •
Parameter Description
Logic Module Propagation Delays
t
t
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
t
t
t
t
f
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
PD1
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
INH
INSU
OUTH
OUTSU
MAX
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX16 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V
Single Module
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input Set-Up
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active
Pulse Width
Flip-Flop (Latch) Asynchronous
Pulse Width
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
Flip-Flop (Latch) Clock Frequency
3, 4
1
2
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
0.5
0.0
1.0
0.0
4.8
6.2
9.5
0.0
0.7
0.0
0.7
CCA
129
1.9
2.0
1.9
2.2
1.1
1.5
1.8
2.2
3.6
= 3.0V, T
v6.1
10.6
‘–2’ Speed
0.5
0.0
1.1
0.0
5.3
6.9
0.0
0.8
0.0
0.8
J
= 70°C)
117
2.1
2.2
2.1
2.4
1.2
1.6
2.0
2.4
4.0
12.0
0.89
‘–1’ Speed
0.6
0.0
1.2
0.0
6.0
7.9
0.0
0.9
0.0
108
2.4
2.5
2.4
2.8
1.4
1.8
2.3
2.7
4.5
‘Std’ Speed
14.1
1.01
1.01
0.7
0.0
1.4
0.0
7.1
9.2
0.0
0.0
40MX and 42MX FPGA Families
2.8
3.0
2.8
3.3
1.6
2.1
2.7
3.2
5.3
94
12.9
19.8
‘–F’ Speed
1.4
0.9
0.0
2.0
0.0
9.9
0.0
1.4
0.0
4.0
4.2
4.0
4.6
2.3
3.0
3.8
4.5
7.5
56
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-59