LTC1235CS Linear Technology, LTC1235CS Datasheet - Page 6

• Manufacturer Part Number: LTC1235CS
• Manufacturer: Linear Technology

Specifications of LTC1235CS

• Number Of Elements: 1
• Monitored Voltage 1 (typ): 4.65V
• Battery Backup Switching: Yes
• Watchdog Timer: Yes
• Chip Enable Signals: Yes
• Reset Active Time: 280ms
• Manual Reset: Yes
• Package Type: SOL
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.5V
• Reset Threshold Voltage (max): 4.75V
• Reset Threshold Voltage (min): 4.5V
• Power Dissipation: 500mW
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Power Fail Detection: Yes
• Mounting: Surface Mount
• Pin Count: 16
• Supply Current: 1.5mA
• Lead Free Status / Rohs Status: Not Compliant

LTC1235
PIN FUNCTIONS
V
V
Logic controls M2. If the status is high, auxiliary power,
connected to V
status is low, the Memory Logic keeps M2 off and V
is in Battery Saving Mode. If backup battery or auxiliary
power is not used, V
V
pass with a capacitor of 0.1μF or greater. During normal
operation, V
power switch, M1, which can deliver up to 50mA and has a
typical on resistance of 5Ω. When V
the status of the BACKUP pin stored in Memory Logic
controls M2. If the status is high, the Memory Logic turns
on M2 and V
M2. If the status is low, the Memory Logic keeps M2 off
and V
are not used, connect V
V
bypassed with a 0.1μF capacitor.
GND (Pin 4): Ground pin.
BATT ON (Pin 5): Battery on logic output from comparator
C2. BATT ON goes low when V
to V
base drive for an external PNP transistor to increase the
output current above the 50mA rating of V
goes high when V
BACKUP pin stored in Memory Logic is high and V
switched to V
LOW LINE (Pin 6): Logic output from comparator C1.
LOW LINE indicates a low line condition at the V
When V
typically), LOW LINE goes low. As soon as V
the reset voltage threshold, LOW LINE returns high (see
Figure 1). LOW LINE goes low when V
(see Table 1).
PB RST (Pin 7): Logic input for direct connection to a push-
button. The push-button reset input requires an active low
signal. Internally, this input signal is debounced and timed
for a minimum of 40ms. When this condition is satisfi ed,
the reset pulse generator forces RESET to active low. The
RESET signal will remain active low for a minimum of 140ms
6
OUT
BATT
BATT
CC
CC
(Pin 3): +5V supply input. The V
(Pin 2): Voltage output for backed up memory. By-
, the status of the BACKUP pin stored in the Memory
OUT
(Pin 1): Backup battery input. When V
. The output typically sinks 35mA and can provide
CC
is in Battery Saving Mode. If V
falls below the reset voltage threshold (4.65V
OUT
OUT
BATT
BATT
obtains power from V
is internally switched to V
CC
.
is delivered to V
falls below V
BATT
OUT
should be connected to GND.
to V
OUT
CC
BATT
is internally connected
.
CC
OUT
CC
CC
, if the status of the
is lower than V
drops below V
through M2. If the
CC
through an NMOS
OUT
pin should be
OUT
CC
CC
BATT
rises above
falls below
and V
. BATT ON
CC
through
OUT
input.
BATT
BATT
BATT
OUT
is
,
from the moment the push-button reset input is released
from logic low level. Pulled to V
Backup (Pin 8): Logic input to control the PMOS switch,
M2, when V
through the reset voltage threshold, the status of the
BACKUP pin (logic low or logic high) is latched in Memory
Logic and used to turn on or off M2 when V
V
the Memory Logic turns on M2 when V
greater than V
pin is low, the Memory Logic keeps M2 off even after V
falls below V
be pulled high by an internal pullup and the LTC1235 will
provide battery backup when V
PFI (Pin 9): Power Failure Input. PFI is the noninverting
input to the Power Fail Comparator, C3. The inverting input
is internally connected to a 1.3V reference. The Power
Failure Output remains high when PFI is above 1.3V and
goes low when PFI is below 1.3V. Connect PFI to GND or
V
PFO (Pin 10): Power Failure Output from C3. PFO remains
high when PFI is above 1.3V and goes low when PFI is
below 1.3V. When V
down and PFO is forced low.
WDI (Pin 11): Watchdog Input, WDI, is a three level
input. Driving WDI either high or low for longer than the
watchdog time-out period, forces both RESET and WDO
low. Floating WDI disables the Watchdog Timer. The timer
resets itself with each transition of the Watchdog Input
(see Figure 11).
CE OUT (Pin 12): Logic output from the Chip Enable gating
circuit. When V
OUT is a buffered replica of CE IN. When V
the reset voltage threshold CE OUT is forced high (see
Figure 6).
CE IN (Pin 13): Logic input to the Chip Enable gating cir-
cuit. CE IN can be derived from microprocessor’s address
line and/or decoder output. See Applications Information
Section and Figure 6 for additional information.
WDO (Pin 14): Watchdog logic output. When the watch-
dog input remains either high or low for longer than the
watchdog time-out period, WDO goes low. WDO is set
OUT
BATT
. If the latched status of the BACKUP pin is high,
when C3 is not used.
CC
BATT
BATT
CC
is lower than V
. If the BACKUP pin is left fl oating it will
is above the reset voltage threshold, CE
. If the latched status of the BACKUP
CC
is lower than V
BATT
CC
CC
with 60k.
falls.
. While V
CC
BATT
falls to 50mV
, C3 is shut
CC
CC
CC
is falling
is below
is below
1235fa
CC