CY2DP814SC Cypress Semiconductor Corp, CY2DP814SC Datasheet - Page 3

• Manufacturer Part Number: CY2DP814SC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY2DP814SC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07060 Rev. *B
Maximum Ratings
Storage Temperature: .................................–65 C to +150 C
Ambient Temperature:................................... –40 C to +85 C
Supply Voltage to Ground Potential
(Inputs and V
Supply Voltage to Ground Potential
Table 1. EN1 EN2 Function Table
Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS
Table 3. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
Table 4. Power Supply Characteristics
Table 5. D.C. Electrical Characteristics: 3.3V–LVDS Input
I
I
V
I
I
I
Notes:
Parameter
Parameter
CCD
C
V
IH
IL
I
1.
2.
CONFIG Pin 2 Binary Value
ID
IC
Ground
Ground
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
V
V
CC
CC
EN1
H
H
L
L
Dynamic Power Supply Current V
Total Power Supply Current
CC
Magnitude of Differential Input Voltage
Common-Mode of Differential Input Voltage
IV
Input High Current
Input Low Current
Input High Current
Enable Logic
Input Condition
1
0
ID
only)....................................... –0.3V to 4.6V
I (min. and max.)
Description
[1][2]
IN+ Pin 6
IN+ Pin 6
IN+ Pin 6
IN+ Pin 6
IN- Pin 7
IN- Pin 7
IN- Pin 7
IN- Pin 7
Description
EN2
H
H
L
L
LVTTL in LVCMOS
LVDS
LVPECL
Input Receiver Family
Input toggling 50% Duty Cycle, Outputs Loaded
V
Input toggling 50% Duty Cycle, Outputs Loaded,
fL= 100 MHz
DD
DD
LVTTL/LVCMOS INPUT LOGIC
= Max.
= Max.
IN+
H
H
H
X
Input Logic
Input
Input
Input
Input
V
V
V
DD
DD
DD
Single ended, non-inverting, inverting, void of bias resistors.
Low voltage differential signaling
Low voltage pseudo (positive) emitter coupled logic
Input
Test Conditions
= Max., V
= Max.
= Max.
(Outputs only) ........................................ –0.3V to V
DC Input Voltage ................................... –0.3V to V
DC Output Voltage................................. –0.3V to V
Power Dissipation........................................................ 0.75W
IN–
IN
X
L
L
L
Conditions
= V
DD
(max.)
Input Receiver Type
Output Logic Q pins
V
V
IN
IN
QnA
= V
= V
H
H
H
Z
ComLink™ Series
Min.
DD
SS
Invert
Invert
True
True
Outputs
IVIDI
Min. Typ. Max. Unit
100
Typ. Max.
1.5
/2
90
CY2DP814
±10 ±20
(IVIDI /2)
±0
100
2.0 mA/MHz
2.4–
QnB
Page 3 of 9
L
L
L
Z
DD
DD
DD
600 mV
±20
±20
Unit
+ 0.3V
+ 0.3V
+ 0.9V
mA
uA
uA
uA
V