WJCE6353 Intel, WJCE6353 Datasheet - Page 25

• Manufacturer Part Number: WJCE6353
• Description: COFDM Terrestrial Demodulator 64-Pin LQFP
• Manufacturer: Intel

Specifications of WJCE6353

• Pin Count: 64
• Screening Level: Commercial
• Package Type: LQFP
• Package: 64LQFP
• Operating Temperature: -10 to 80 °C
• Lead Free Status / Rohs Status: Compliant

4.5.1.3
To calculate the power dissipated in a crystal the following equation can be used.
Equation 3 -
Pc = power dissipated in crystal at resonant frequency (W)
Vpp = maximum peak to peak output swing of amplifier is 1.8V for all CVdd
Zin = crystal network impedance (see Equation 2)
4.5.1.4
Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with Equation 4
below.
Equation 4 -
Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.
Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the resulting
crystal load capacitance C
are 15pF, 20pF and 30pF). The crystal will then operate very near its specified frequency.
Equation 5 -
C
(including any socket used) and the printed circuit board’s track-to-track capacitance.
C
If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’s recom-
mended C
frequency stability. Smaller values of C
taken that C
to quote C
conditions, at the desired frequency.
Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is not
feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain condition is still
satisfied. This must be done using Equation 1.
4.5.1.5
•
•
•
•
Note:
par12
par12
On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. Other
signal tracks must not be allowed to cross through this area. The component tracks should preferably be ringed by
a ground track connected to the chip ground (0V) on adjacent pins either side of the crystal pins. It is also
advisable to provide a ground plane for the circuit to reduce noise.
External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0V and CVdd) and
current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cell’s amplitude
clamping circuit.
An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To limit the
current taken from the signal source a resistor should be placed between the clock source and XTI. The
recommended value for this series resistor is 470 Ω for a clock signal switching between 0V and CVdd. The
current the clock source needs to source/sink is then ≤ 1.9 mA. The XTO pin must be left unconnected in this
configuration. See Figure 15.
AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty cycle of the
≈ 2pF.
=
2 >
parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pin capacitance
L
L
may be acceptable. Larger values of C
to the crystal manufacturer who can then cut a crystal to order which will resonate, under the specified load
L
Calculating Crystal Power Dissipation
Capacitor Values
Oscillator/Clock Application Notes
does not fall outside the crystal pulling range or the circuit may fail to start up altogether. It is also possible
C
C
- C
2
1
C
P
in
L
c
> 0.5
=
=
= C
8.Z
V
out
C
C
pp
out
L
out
(see Equation 5) is close to the crystal manufacturers recommended C
in
2
=
+ C
. C
in
in
+ C
g
A
L
m
par12
tend to reduce startup time and crystal power dissipation. Care must however be
-
R
2
f
-
Z
1
o
L
tend to reduce the influence of circuit variations and tolerances on
.
Intel Corporation
(2.π.f)
CE6353
1
2
.ESR when: C
1
= C
2
= C
out
- C
par
L
(standard values for C
Data Sheet
25
L