AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet - Page 28
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AT86RF211SAHW
Manufacturer Part Number
AT86RF211SAHW
Description
Manufacturer
Atmel
Datasheet
1.AT86RF211SAHW.pdf
(64 pages)
Specifications of AT86RF211SAHW
Lead Free Status / Rohs Status
Compliant
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Figure 4-26. Clock Recovery
4.4.2
28
0894C–WIRE–11/08
DATAMSG
DATACLK
Data Rate Programming
depending on the previous DATA transition; the clock is moved later or sooner, depending on the gap
between CLOCK and DATA.
For example:
If DATARATE = 50 kbps, which is equivalent to a duration of 200 × T for 1 bit, with
T = 100 ns = base clock period.
If DATATOL = 4% × DATARATE = 8 × T.
This value must only be programmed when the DATA clock is needed on the chip’s DATACLK output
pin.
The DATA rate can be programmed from 1 to 100 kbps with 14 bits of the CTRL2 register.
DATARATE is the period of the data rate and can be programmed with a resolution given by the crystal
oscillator period:
Table 4-8
Table 4-8.
DATARATE[13:0]
(102)
(205)
(even number)
(odd numbers)
(534)
(1024)
(1067)
(2135)
(4269)
(10246)
• 10.245 MHz oscillator, period = T = 97.6 ns
10
10
10
10
10
10
10
10
provides examples of data rate values with the 10.245 MHz oscillator:
10
Data Rate Values with an 10.245 MHz Oscillator
10
200T
Expected Values
Rate
100 kbps
50 kbps
19.2 kbps
10 kbps
9.6 kbps
4.8 kbps
2.4 kbps
1 kbps
Tol = 8T
Synchronized Values with DATAMSG
Period
1 bit ~ 102 × T
1 bit ~ (205-1) × T
1 bit ~ (even number) × T
1 bit ~ (odd numbers -1) × T
1 bit ~ 534 × T
1 bit ~ 1024 × T
1 bit ~ (1067-1) × T
1 bit ~ (2135-1) × T
1 bit ~ (4269 -1)× T
1 bit ~ 10246 × T
Tol = 8T
Expected Values
e2v semiconductors SAS 2008
AT86RF211S
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