AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet - Page 3
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AT86RF211SAHW
Manufacturer Part Number
AT86RF211SAHW
Description
Manufacturer
Atmel
Datasheet
1.AT86RF211SAHW.pdf
(64 pages)
Specifications of AT86RF211SAHW
Lead Free Status / Rohs Status
Compliant
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3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.2.2
3.3
e2v semiconductors SAS 2008
Low-power Standby Modes
Asynchronous Transparent Transmit Mode
Faster RSSI
Digital Signal Output DIGOUT
Charge and Hold Data Slicer Mode
PDN Mode
XTAL Running
The ADC clock period can now be decreased from 12 µs to 1.5 µs. Faster channel scanning in multi-
channel applications or LBT (Listen Before Transmit) is then possible, as well as ASK demodulation for
low data rates.
Pin 17 was previously reserved and not connected, but can now deliver several signals:
After a charge phase, the comparison threshold of the data slicer is stored in the external SKFILT capac-
itor. This is an additional and very easy way to implement a transparent NRZ UART mode, for instance.
This is a very low power mode. Only the control interface is powered and I
The XTO remains active for short start-up-time applications at 150 µA, rising to 950 µA typical if the
10.245 MHz signal is buffered on the DIGOUT pin, assuming that the load is 10 pF.
The chip is set-up by the MCU to act as transmitter. It then acts like a pipe in which any data entering
DATAMSG is immediately radiated on the antenna. No data is stored or processed on the chip. The
transmission is asynchronous.
• Divided XTAL reference clock
• Carrier detection when RSSI is above predefined TRSSI
• XTO running flag
• 455 kHz signal from the discriminator PLL
• Receive mode flag
• 1 kHz reference clock of the wake-up timer
• Lock detect flag PLLL of the main PLL
CC
is as low as 500 nA typical.
0894C–WIRE–11/08
AT86RF211S
3
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