AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet - Page 35

• Manufacturer Part Number: AT86RF211SAHW
• Manufacturer: Atmel

Specifications of AT86RF211SAHW

• Lead Free Status / Rohs Status: Compliant

4.6.1.3
Figure 4-31. Read Chronogram: Complete Read Cycle from a 10-bit Register
e2v semiconductors SAS 2008
SLE
SCK
SDATA
SDATA
Direction
READ Mode (R/W = 0)
The address and R/W bits are clocked on the rising edge of SCK and the data bits are changed on the
falling edge of SCK. The register’s MSB is the first bit read.
The SDATA I/O pin is switched from input to output on the edge following the 1 clocking the R/W bit.
It is possible to stop reading a register (by reverting SLE to 1) at any time.
If an attempt is detected to read more bits than the register capacity, SDATA is clamped to 0.
If the address of a register is not valid, SDATA is set to 1 during the first 32 SCK periods, and then to 0
during all the extra periods.
SDATA is switched back to the input state when SLE reverts to 1.
Figure 4-32. Read Chronogram: Partial Read Cycle, Reading 2 Bits
A[3]
A[2 ]
INPUT
A[1]
SLE
SCK
SDATA
SDATA
Mode
A[0]
R/W
D[9 ]
A[3]
D[8]
A[2]
INPUT
D[7]
A[1]
D[6]
A[0]
D[5]
OUTPUT
R/W
D[4]
D[31]
OUTPUT
D[3]
D[30]
D[2]
D[1]
INPUT
D[0]
0894C–WIRE–11/08
AT86RF211S
INPUT
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